Fairchild HUF76129D3, HUF76129D3S service manual

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HUF76129D3, HUF76129D3S

Data Sheet January 2003

20A, 30V, 0.016 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs

These N-Channel pow er MOSFETs
are manufactured using the
innovati ve UltraFET™ process.

This advanced process technology
achieves the lowest possible on-resistance per silicon ar ea,
resultin g in outstanding performance. This device is capab le
of withstanding hi gh energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was design ed for use in applicati ons where power
efficiency is important, such as switching regulators,
switchi ng converters, motor drivers, relay drivers , low­voltage bus switches, and power manage me nt i n po rtab le
and battery-operated products.

Formerly developmental ty pe TA76129.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76129D3 TO-251AA 76129D
HUF76129D3S TO-252AA 76129D

NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76129D3ST.

Features

• Logic Level Gate Drive

• 20A, 30V

• Ultra Low On-Resistance, r

• Temperatur e Compensating PSPICE

• Temperatur e Compensating SABER

DS(ON)

= 0.016Ω

®

Model

©

Mode

• Thermal Impedance SPICE Model

• Thermal Impedance SABER Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

Packaging

(FLANGE)

DRAIN

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

GATE

SOURCE

DRAIN

(FLANGE)

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

HUF76129D3, HUF76129D3S

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gat e Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 V
30 V

±20 V

Drain Curr e nt

Continuous (T

Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

C

Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

, T

J

STG

D
D
D

DM

AS

D

20
20
20

Figure 4

Figures 6, 17, 18

105

.83

-55 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Rati ngs” may cause permane nt damage to the device. This is a stress only rating and oper ation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

A
A
A

W

W/oC

o

C

o

C

o

C

NOTE:

= 25oC to 150oC.

1. T

J

Electrical Specifications TA = 25

o

C, Unless Othe r wis e Specifi ed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain t o Source Breakdown Voltage BV
Zero Gat e V ol tag e D rain Curre nt I

Gate to Sour c e Le ak ag e C urr e nt I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

GS(TH)VGS

DS(ON)ID

THERMAL SPECIFICATIONS

Thermal R esis ta nc e Ju ncti on to Case R
Thermal Resistance Junction to Ambient R
SWITCHING SPECIFICATIONS (V

GS

= 4.5V)
Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t

DSSID

DSS

GSS

θJC
θJA

ON

r

f

OFF

= 250µA, VGS = 0V (Figure 12) 30 - - V
VDS = 25V, VGS = 0V - - 1 µA
V

= 25V, VGS = 0V, TC = 150oC--250µA

DS

VGS = ±20V - - ±100 nA

= VDS, ID = 250µA (Figur e 11) 1 - 3 V

= 20A, VGS = 10V (Figure 9, 10) - 0. 014 0.01 6 Ω
I

= 20A, VGS = 5V (Figure 9) - 0.0175 0.02 1 Ω

D

I

= 20A, VGS = 4.5V (Figure 9) - 0.0195 0.023 Ω

D

(Figur e 3) - - 1. 20
TO-251, TO-252 - - 100

VDD = 15V, ID ≅ 20A, RL = 0.75Ω,
V

= 4.5V, RGS = 10Ω

GS

(Figures 15, 21 , 22)

--275ns

-20-ns

o
o

C/W
C/W

-165- ns

-30-ns

-54-ns

--125ns

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

HUF76129D3, HUF76129D3S

Electrical Specifications TA = 25

o

C, Unless Othe r wis e Specifi ed (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charg e Q
Gate Charge at 5V Q
Threshold Gat e Ch arg e Q
Gate to Source Gate Charg e Q
Gate to Drain “M ill er ” Cha tg e Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(5)

g(TH)

ISS
OSS
RSS

VDD = 15V, ID ≅ 20A, RL = 0.75Ω,
V
(Figures 16, 21 , 22)

r

f

VGS = 0V to 5V - 22 26 nC
VGS = 0V to 1V - 1.4 1.7 nC

gs
gd

VDS = 25V, VGS = 0V, f = 1MHz
(Figur e 13 )

= 10V, RGS = 10Ω

GS

= 0V to 10V VDD = 15V, ID ≅ 20A,

R

= 0.75Ω

L

I

= 1.0mA

g(REF)

(Figures 14, 1 9, 20)

--80ns

-7-ns

-47-ns

-60-ns

-54 -ns

--110ns

-3846nC

-3.70- nC

-11.20- nC

-1425- pF

-720- pF

-170- pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Vol tage V
Reverse Recovery Time t
Reverse Recovered Charge Q

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

SD

rr

RR

ISD = 20A - - 1.25 V
ISD = 20A, dISD/dt = 100A/µs--72ns
ISD = 20A, dISD/dt = 100A/µs - - 107 nC

25

20

VGS=10V

VGS=4.5V

150

125

15

10

, DRAIN CURRENT (A)

D

I

5

0

25 50 75 100 125

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE

TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

HUF76129D3, HUF76129D3S

Typical Performance Curves (Continued)

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

JC

θ

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

2000

100

, PEAK CURRENT (A)

DM

I

-5

10

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

10

-5

10

VGS = 10V

-4

10

-3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

VGS = 5V

-4

10

10

-3

-2

10

t, RECT ANGULAR PULSE DURATION (s)

-2

10

t, PULSE WIDTH (s)

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

-1

10

P

DM

t

1

t

2

1/t2

x R

JC

JC

θ

θ

0

10

TC = 25oC

FOR TEMPERATURE S
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

150 - T

I = I

25

10

C

125

0

+ T

C

1

10

1

10

FIGURE 4. PEAK CURRENT CAPABILITY

, AVALANCHE CURRENT (A)
I

500

100

AS

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

DSS

- VDD)

DSS

- VDD) +1]

STARTING TJ = 25oC

10

STARTING TJ = 150oC

1

0.01

0.1

1 10 100

tAV, TIME IN AVALANCHE (ms)

1000

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE

LIMITED BY r

1

DS(ON)

BV

DSS MAX

= 30V

10

, DRAIN TO SOURCE VOLT AGE (V)

V

DS

TJ = MAX RATED

= 25oC

T

C

100µs

1ms

10ms

1001

NO TE: Refer to Fairchild App lication Notes AN9321 and AN9322.

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1