Fairchild HUF76129D3, HUF76129D3S service manual

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HUF76129D3, HUF76129D3S

Data Sheet January 2003

20A, 30V, 0.016 Ohm, N-Channel, Logic
Level UltraFET Power MOSFETs

These N-Channel pow er MOSFETs
are manufactured using the
innovati ve UltraFET™ process.

This advanced process technology
achieves the lowest possible on-resistance per silicon ar ea,
resultin g in outstanding performance. This device is capab le
of withstanding hi gh energy in the avalanche mode and the
diode exhibits very low reverse recovery time and stored
charge. It was design ed for use in applicati ons where power
efficiency is important, such as switching regulators,
switchi ng converters, motor drivers, relay drivers , low­voltage bus switches, and power manage me nt i n po rtab le
and battery-operated products.

Formerly developmental ty pe TA76129.

Ordering Information

PART NUMBER PACKAGE BRAND

HUF76129D3 TO-251AA 76129D
HUF76129D3S TO-252AA 76129D

NOTE: When ordering, use the entire part number. Add the suffix T to
obtain the TO-252AA variant in tape and reel, e.g., HUF76129D3ST.

Features

• Logic Level Gate Drive

• 20A, 30V

• Ultra Low On-Resistance, r

• Temperatur e Compensating PSPICE

• Temperatur e Compensating SABER

DS(ON)

= 0.016Ω

®

Model

©

Mode

• Thermal Impedance SPICE Model

• Thermal Impedance SABER Model

• Peak Current vs Pulse Width Curve

• UIS Rating Curve

• Related Literature

- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”

Symbol

D

G

S

Packaging

(FLANGE)

DRAIN

JEDEC TO-251AA JEDEC TO-252AA

SOURCE

DRAIN

GATE

GATE

SOURCE

DRAIN

(FLANGE)

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

HUF76129D3, HUF76129D3S

Absolute Maximum Ratings T

= 25oC, Unless Otherwise Specified

C

UNITS

Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

Drain to Gat e Voltage (R

= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V

GS

Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V

DSS

DGR

GS

30 V
30 V

±20 V

Drain Curr e nt

Continuous (T

Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

C

Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I

Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I

Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P

Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

, T

J

STG

D
D
D

DM

AS

D

20
20
20

Figure 4

Figures 6, 17, 18

105

.83

-55 to 150

Maximum Temperature for Soldering

Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T

Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T

CAUTION: Stresses above those listed in “Absolute Maximum Rati ngs” may cause permane nt damage to the device. This is a stress only rating and oper ation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

L

pkg

300
260

A
A
A

W

W/oC

o

C

o

C

o

C

NOTE:

= 25oC to 150oC.

1. T

J

Electrical Specifications TA = 25

o

C, Unless Othe r wis e Specifi ed

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

OFF STATE SPECIFICATIONS

Drain t o Source Breakdown Voltage BV
Zero Gat e V ol tag e D rain Curre nt I

Gate to Sour c e Le ak ag e C urr e nt I

ON STATE SPECIFICATIONS

Gate to Source Threshold Voltage V
Drain to Source On Resistance r

GS(TH)VGS

DS(ON)ID

THERMAL SPECIFICATIONS

Thermal R esis ta nc e Ju ncti on to Case R
Thermal Resistance Junction to Ambient R
SWITCHING SPECIFICATIONS (V

GS

= 4.5V)
Turn-On Time t
Turn-On Delay Time t

d(ON)

Rise Time t
Turn-Off Delay Time t

d(OFF)

Fall Time t
Turn-Off Time t

DSSID

DSS

GSS

θJC
θJA

ON

r

f

OFF

= 250µA, VGS = 0V (Figure 12) 30 - - V
VDS = 25V, VGS = 0V - - 1 µA
V

= 25V, VGS = 0V, TC = 150oC--250µA

DS

VGS = ±20V - - ±100 nA

= VDS, ID = 250µA (Figur e 11) 1 - 3 V

= 20A, VGS = 10V (Figure 9, 10) - 0. 014 0.01 6 Ω
I

= 20A, VGS = 5V (Figure 9) - 0.0175 0.02 1 Ω

D

I

= 20A, VGS = 4.5V (Figure 9) - 0.0195 0.023 Ω

D

(Figur e 3) - - 1. 20
TO-251, TO-252 - - 100

VDD = 15V, ID ≅ 20A, RL = 0.75Ω,
V

= 4.5V, RGS = 10Ω

GS

(Figures 15, 21 , 22)

--275ns

-20-ns

o
o

C/W
C/W

-165- ns

-30-ns

-54-ns

--125ns

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

HUF76129D3, HUF76129D3S

Electrical Specifications TA = 25

o

C, Unless Othe r wis e Specifi ed (Continued)

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

SWITCHING SPECIFICATIONS (VGS = 10V)

Turn-On Time t
Turn-On Delay Time t
Rise Time t
Turn-Off Delay Time t
Fall Time t
Turn-Off Time t

GATE CHARGE SPECIFICATIONS

Total Gate Charg e Q
Gate Charge at 5V Q
Threshold Gat e Ch arg e Q
Gate to Source Gate Charg e Q
Gate to Drain “M ill er ” Cha tg e Q

CAPACITANCE SPECIFICATIONS

Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C

ON

d(ON)

d(OFF)

OFF

g(TOT)VGS

g(5)

g(TH)

ISS
OSS
RSS

VDD = 15V, ID ≅ 20A, RL = 0.75Ω,
V
(Figures 16, 21 , 22)

r

f

VGS = 0V to 5V - 22 26 nC
VGS = 0V to 1V - 1.4 1.7 nC

gs
gd

VDS = 25V, VGS = 0V, f = 1MHz
(Figur e 13 )

= 10V, RGS = 10Ω

GS

= 0V to 10V VDD = 15V, ID ≅ 20A,

R

= 0.75Ω

L

I

= 1.0mA

g(REF)

(Figures 14, 1 9, 20)

--80ns

-7-ns

-47-ns

-60-ns

-54 -ns

--110ns

-3846nC

-3.70- nC

-11.20- nC

-1425- pF

-720- pF

-170- pF

Source to Drain Diode Specifications

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Source to Drain Diode Vol tage V
Reverse Recovery Time t
Reverse Recovered Charge Q

Typical Performance Curves

1.2

1.0

0.8

0.6

0.4

0.2

POWER DISSIPATION MULTIPLIER

0

0 25 50 75 100 150

TA, AMBIENT TEMPERATURE (oC)

SD

rr

RR

ISD = 20A - - 1.25 V
ISD = 20A, dISD/dt = 100A/µs--72ns
ISD = 20A, dISD/dt = 100A/µs - - 107 nC

25

20

VGS=10V

VGS=4.5V

150

125

15

10

, DRAIN CURRENT (A)

D

I

5

0

25 50 75 100 125

TC, CASE TEMPERATURE (oC)

FIGURE 1. NORMALIZED PO WER DISSIPATION vs CASE

TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs

CASE TEMPERATURE

HUF76129D3, HUF76129D3S

Typical Performance Curves (Continued)

2

DUTY CYCLE - DESCENDING ORDER

0.5

1

0.2

0.1

0.05

0.02

0.01

0.1

, NORMALIZED

JC

θ

Z

THERMAL IMPEDANCE

SINGLE PULSE

0.01

2000

100

, PEAK CURRENT (A)

DM

I

-5

10

TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION

10

-5

10

VGS = 10V

-4

10

-3

10

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

VGS = 5V

-4

10

10

-3

-2

10

t, RECT ANGULAR PULSE DURATION (s)

-2

10

t, PULSE WIDTH (s)

NOTES:
DUTY FACTOR: D = t

PEAK TJ = PDM x Z

-1

10

-1

10

P

DM

t

1

t

2

1/t2

x R

JC

JC

θ

θ

0

10

TC = 25oC

FOR TEMPERATURE S
ABOVE 25

o

C DERATE PEAK

CURRENT AS FOLLOWS:

150 - T

I = I

25

10

C

125

0

+ T

C

1

10

1

10

FIGURE 4. PEAK CURRENT CAPABILITY

, AVALANCHE CURRENT (A)
I

500

100

AS

If R = 0
tAV = (L)(IAS)/(1.3*RATED BV

If R ≠ 0

= (L/R)ln[(IAS*R)/(1.3*RATED BV

t

AV

DSS

- VDD)

DSS

- VDD) +1]

STARTING TJ = 25oC

10

STARTING TJ = 150oC

1

0.01

0.1

1 10 100

tAV, TIME IN AVALANCHE (ms)

1000

100

10

, DRAIN CURRENT (A)

D

I

OPERATION IN THIS
AREA MAY BE

LIMITED BY r

1

DS(ON)

BV

DSS MAX

= 30V

10

, DRAIN TO SOURCE VOLT AGE (V)

V

DS

TJ = MAX RATED

= 25oC

T

C

100µs

1ms

10ms

1001

NO TE: Refer to Fairchild App lication Notes AN9321 and AN9322.

FIGURE 5. FORWARD BIAS SAFE OPERATING AREA

FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING

CAPABILITY

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

HUF76129D3, HUF76129D3S

Typical Performance Curves (Continued)

60

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

45

30

, DRAIN CURRENT (A)

D

I

15

0

0231

, GATE TO SOURCE VOLTAGE (V)

V

GS

25oC

-55oC

V

DD

150oC

= 15V

4

60

45

30

, DRAIN CURRENT (A)

, DRAIN CURRENT (A)

15

D

D

I

I

0

012345

VDS, DRAIN TO SOURCE VOLTAGE (V)

VDS, DRAIN TO SOURCE VOLTAGE (V)

= 10V

V

GS

= 5V

V

GS

V

= 4.5V

GS

VGS = 4V

FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS

30

27

24

ID = 5A

21

, DRAIN TO SOURCE

18

ON RESISTANCE (mΩ)

DS(ON)

r

15

12

26108

ID = 20A

ID = 10A

4

, GATE TO SOURCE VOLTAGE (V)

V

GS

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

1.6

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

V

= 10V, ID = 20A

GS

1.4

1.2

1.0

ON RESISTANCE

0.8

NORMALIZED DRAIN TO SOURCE

0.6

-80 0 40

-40
TJ, JUNCTION TEMPERATURE (oC)

PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX

VGS = 3.5V

VGS = 3V

80

120

160

FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE

VOLTAGE AND DRAIN CURRENT

1.2

1.1

1.0

0.9

0.8

NORMALIZED GATE

THRESHOLD VOLTAGE

0.7

0.6

-80 0 40 160

-40
TJ, JUNCTION TEMPERATURE (oC)

VGS = VDS, ID = 250µA

80

120

FIGURE 11. NORMALIZED GATE THRESHOLD VOL TAGE vs

JUNCTION TEMPERATURE

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

FIGURE 10. NORMALIZED DRAIN TO SOURCE ON

RESISTANCE vs JUNCTION TEMPERATURE

1.15
ID = 250µA

1.10

1.05

1.00

BREAKDOWN VOLTAGE

0.95

NORMALIZED DRAIN TO SOURCE

0.90

-80 0 40 160

-40
T

, JUNCTION TEMPERATURE (oC)

J

80

120

FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN

VOLTAGE vs JUNCTION TEMPERATURE

HUF76129D3, HUF76129D3S

Typical Performance Curves (Continued)

2000

1600

1200

C

C

ISS

OSS

V

= 0V, f = 1MHz

GS

= CGS + C

C

ISS

C

= C

RSS

C

≈ CDS + C

OSS

GD

GD

GD

800

C, CAPACITANCE (pF)

400

C

RSS

0

0101520

5

V

, DRAIN TO SOURCE VOLTAGE (V)

DS

25

FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

500

VGS = 4.5V, VDD = 15V, ID = 20A, RL= 0.75Ω

400

300

200

SWITCHING TIME (ns)

100

0

10

20 30 40 500

RGS, GATE TO SOURCE RESISTANCE (Ω)

t

d(OFF)

t

r

t

d(ON)

t

f

10

VDD = 15V

8

6

4

WAVEFORMS IN
DESCENDING ORDER:

2

, GATE TO SOURCE VOLTAGE (V)

GS

V

30

0

10

Q

, GATE CHARGE (nC)

g

20

ID = 20A

= 10A

I

D

= 2A

I

D

300

40

NOTE: Refer to Fairchild Application Notes 7254 and 7260.

FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT

GATE CURRENT

300

VGS = 10V, VDD = 15V, ID = 20A, RL= 0.75Ω

250

t

200

150

100

SWITCHING TIME (ns)

50

0

10

20 30 40 500

RGS, GATE TO SOURCE RESISTANCE (Ω)

d(OFF)

t

f

t

r

t

d(ON)

FIGURE 15. SWITCHING TIME vs GATE RESISTANCE FIGURE 16. SWITCHING TIME vs GATE RESISTANCE

Test Circuits and Waveforms

V

DS

BV

DSS

L

VARY t

TO OBTAIN

P

REQUIRED PEAK I

V

GS

AS

R

G

+

V

DD

-

DUT

0V

P

I

AS

0.01Ω

0

t

FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 18. UNCLAMPED ENERGY WAVEFORMS

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

t

P

I

AS

t

AV

V

DS

V

DD

HUF76129D3, HUF76129D3S

Test Circuits and Waveforms (Continued)

V

DS

R

L

V

GS

DUT

I

g(REF)

FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS

+

V

-

DD

V

DD

V

0

I

g(REF)

0

GS

V

= 1V

GS

Q

g(TH)

Q

g(TOT)

V

DS

Q

g(5)

V

= 10

GS

VGS = 5V

V

DS

R

L

V

GS

R

GS

V

GS

DUT

+

V

DD

-

V

DS

0

V

GS

10%

0

t

d(ON)

90%

t

ON

50%

t

10%

r

PULSE WIDTH

FIGURE 21. SWITCHING TIME TEST CIRCUIT FIGURE 22. SWITCHING TIME WAV EFORM

t

d(OFF)

90%

t

OFF

50%

t

f

90%

10%

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

E

HUF76129D3, HUF76129D3S

PSPICE Electrical Model

SUBCKT HUF76129D 2 1 3 ; REV April 1998

CA 12 8 1.95 e - 9
CB 15 14 1.85e-9
CIN 6 8 1.31e-9

DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 32
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1

GATE

IT 8 17 1
LDRAIN 2 5 1e- 9

LGATE 1 9 2.20e- 9
LSOURCE 3 7 3.03e-9

MMED 16 6 8 8 MMEDM OD
MSTR O 16 6 8 8 M S T ROMOD
MWEAK 16 21 8 8 MWE AKMOD

RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.9e-3
RGATE 9 20 3.5
RLDRAIN 2 5 10
RLGATE 1 9 22
RLSOURCE 3 7 30.3
RSLC1 5 51 RSL CM OD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 10e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

LGATE

1

RLGATE

RGATE

9

CA

-

ESG

+

EVTEMP

+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

13

6
8

10

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

15

CIN

CB

-

+

5
8

-

5

RSLC1

51

+

5

51

-

50
RDRAIN

21

MSTRO

14

ESLC

16

8

MMED

DBREAK

EBREAK

MWEAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

LDRAIN

RLDRAIN

11

+

17
18

DBODY

DRAIN

2

-

LSOURCE

7

RLSOURCE

RVTEMP
19

SOURC

3

-

VBAT

+

22

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*1000),3.5))}
.MODEL DBOD Y M OD D (IS = 1.2e-12 IKF = 8 TIKF = 1e-2 RS = 7.7 e-3 TRS1 = 3e-4 TRS2 = 1e-6 CJO = 2.23e-9 TT = 35e-9 M = 4e-1 XTI =4.75 )

.MODEL DBR EAKMOD D (RS = 9.5e-2 TRS1 = 4e-3 TRS2 = 3e-5 IKF = 1e-1)
.MODEL DPLC A PMOD D (CJO = 1.12e-10 IS = 1e-30 N = 10 M = 6.5e-1 VJ = 1. 45)
.MODEL MMEDMOD NMOS (VTO = 1.87 KP = 5.75 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1)
.MODEL MSTROM OD NMOS (VTO = 2. 15 K P = 90 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.49 KP =2e-2 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10)
.MODEL RBR EA K M OD RES (TC1 = 9.8e-4 TC2 = -1e-10)
.MODEL RD RAINMOD RES (TC1 = 1e -2 TC2 = 1e-5)
.MODEL RSLC M OD RES (TC1 = 1e-6 T C2 = 1.05e-6)
.MODEL RSOURCEMOD RES (TC1 = 2.5e-3 TC2 = 2e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -1.1e-5)
.MODEL RVTE MPMOD RES (T C1 = -1.65e-3 TC2 = 1.45e- 6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -10.0 VOFF= -0.50)
.MODEL S1BM OD V S WITCH (RON = 1e- 5 ROFF = 0.1 VON = -0.50 VOFF= -10.0)
.MODEL S2AM OD V SWITCH (RO N = 1e- 5 ROFF = 0.1 VON = 0.00 VOFF= 0.50)
.MODEL S2BM OD V SWITCH (RO N = 1e- 5 ROFF = 0.1 VON = 0.50 VOFF= 0.00)

.ENDS

NOTE: For further discussi on of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
T emperature Opti ons; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

HUF76129D3, HUF76129D3S

SABER Electrical Model

nom temp=25 deg c 30v LL Ultraf et

REV April 1998
template huf76129D n2 ,n1,n3

electrical n2,n1,n3
{
var i iscl
d..model db odymod = (is=1. 2e-12, xti=4.75, cjo=2.23e-9,tt=35e-8, m=4e-1)
d..model dbreakmod = (is=1e-14)
d..model dp lcapmod = (cjo=1.12e-9,is=1e-30,n=10, m =6.5e-1, vj=1 .45, fc=5e-1)
m..model mmedmod = (type=_n,vto=1.87,kp=5.75,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.15,kp=90,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.49,kp=2e-2,is=1e-30, tox=1)
sw_vcsp.. mo del s1amod = (ron= 1e-5,roff=0. 1,von=-10.0,voff=-0. 5)
sw_vcsp.. mo del s1bmod = (ron= 1e-5,roff=0.1,von=-0.5,voff=10 .0)
sw_vcsp.. mo del s2amod = (ron= 1e-5,roff=0.1,von=0,v off=0.5)
sw_vcsp.. mo del s2bmod = (ron= 1e-5,roff=0.1,von=0.5,voff=0)

c.ca n12 n8 = 1.95e-9
c.cb n15 n14 = 1.85e-9
c.cin n6 n8 = 1.31 e-9

d.dbody n7 n71 = model=dbodymod
d.dbreak n72 n11 = model=dbr eakmod
d.dplcap n10 n5 = m odel=dplcapmod

i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9

l.lgate n1 n9 = 2.2e-9
l.lsource n3 n7 = 3.03e-9

GATE

LGATE

1

RLGATE

RGATE

9

m.mmed n16 n6 n8 n8 = m odel=mmed m od, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=m strongmod, l= 1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w =1u

res.rbreak n17 n18 = 1, tc1=9.8e-4,tc2=-1e-10
res.rdbody n71 n5 =7.7e-3, tc 1=2.5e-3, tc2=1e-6
res.rdbreak n72 n5 =9.5e -2, tc 1=4e-3, tc2=3e-5
res.rdrain n50 n16 = 1.9e-3, tc 1=1e-2,tc2=1e-5
res.rgate n9 n20 = 3.6e-1
res.rldrai n n2 n5 = 10
res.rlgate n1 n9 = 22

CA

res.rlsource n3 n7 = 30.3
res.rslc1 n5 n51 = 1e-6, tc1=1e-6,tc2= -1. 05e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1=2.5e-3,tc2=2e-6
res.rvtemp n18 n19 = 1, tc1=-1.8e-3,tc2=1.1e-5
res.rvthres n22 n8 = 1, tc1=-1.65e-3,tc2=-1.45e-6

-

ESG

+

EVTEMP
+

-

18
22

20

S1A

12

13

8

S1B

EGS EDS

6
8

13

10

RSLC2

6

14
13

+

+

6
8

-

-

DPLCAP

EVTHRES

+

19

8

S2A

S2B

15

CB

CIN

-

+

5
8

-

5

RSLC1

51

50

RDRAIN

21

MSTRO

14

ISCL

16

8

MMED

RDBREAK

72

DBREAK

11

MWEAK

EBREAK

RSOURCE

RBREAK

17 18

IT

8

RVTHRES

+

17
18

-

7

RVTEMP
19

-

+

22

LDRAIN

RLDRAIN

RDBODY

71

DBODY

LSOURCE

RLSOURCE

VBAT

DRAIN

2

SOURCE

3

spe.ebreak n11 n7 n17 n18 = 37
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1 a n6 n12 n13 n8 = model=s 1amod
sw_vcsp.s1 b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2 a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2 b n13 n15 n14 n13 = mod el= s2bmod

v.vbat n22 n19 = dc=1
equations {

i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v (n5,n51))))*((abs(v (n5,n51)*1e6/1000))** 3.5 ))
}
}

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

HUF76129D3, HUF76129D3S

SPICE Thermal Model

REV April 1998

HUF76129D

CTHERM1 th 6 1.10e-5
CTHER M 2 6 5 2.70e- 2
CTHER M 3 5 4 3.90e- 2
CTHER M 4 4 3 1.00e- 2
CTHER M 5 3 2 2.30e- 2
CTHERM6 2 tl 1.80

RTHERM1 th 6 1.00e-4
RTHER M 2 6 5 5.00e- 4
RTHER M 3 5 4 2.90e- 2
RTHER M 4 4 3 4.80e- 1
RTHER M 5 3 2 2.80e- 1
RTHERM6 2 tl 1.00e-1

SABER Thermal Model

Saber thermal model HUF76129D
template thermal_model th tl

thermal_c th, tl
{
ctherm.ctherm1 th c2 = 1.10e-5
ctherm.ctherm2 c2 c3 = 2.70e-2
ctherm.ctherm3 c3 c4 = 3.90e-2
ctherm.ctherm4 c4 c5 = 1.00e-2
ctherm.ctherm5 c5 c6 = 2.30e-2
ctherm.ctherm6 c6 tl = 1.80

rtherm.rtherm1 th c2 = 1.00e-4
rtherm.rtherm2 c2 c3 = 5.00e-4
rtherm.rtherm3 c3 c4 = 2.90e-2
rtherm.rtherm4 c4 c5 = 4.80e-1
rtherm.rtherm5 c5 c6 = 2.80e-1
rtherm.rtherm6 c6 tl = 1.00e-1
}

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

JUNCTION

th

CTHERM1

6

CTHERM2

5

CTHERM3

4

CTHERM4

3

CTHERM5

2

CTHERM6

CASE

tl

©2003 Fairchild Semiconductor Corporation HUF76129D3, HUF76129D3S Rev. B1

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PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Adva nce Information Formative or In

Design

Preliminary First Production This datasheet contains preliminary data, and

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Obsolete Not In Producti on This datasheet contains specifications on a product

This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.

supple m entary data will be published at a later date.
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changes at any time without notice in order to improve
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The datasheet is printed for reference information only.

Rev. I2