Fairchild HUF75945G3, HUF75945P3, HUF75945S3ST service manual

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HUF75945G3, HUF75945P3, HUF75945S3ST
Data Sheet December 2001
38A, 200V, 0.071 Ohm, N-Channel, UltraFET® Power MOSFETs
Packaging
JEDEC TO-247
SOURCE
DRAIN
GATE
DRAIN (TAB)
JEDEC TO-220AB JEDEC TO-263AB
SOURCE
DRAIN
GATE
DRAIN
(FLANGE
Features
• Ultra Low On-Resistance
• Simulation Models
- Temperature Compensated PSPICE® and SABER™ Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Cu rrent vs Pulse Width Curve
• UIS Rating Curve
DS(ON)
= 0.071Ω, V
GS
= 10V
GATE
DRAIN (FLANGE)
SOURCE
Symbol
G
S
Absolute Maximum Ratings
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain to Gate Voltage (R
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
Drain Current
Continuous (T
Continuous (TC = 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
NOTES:
= 25oC to 150oC.
1. T
J
CAUTION: Stresses above those listed in “ Absolute M aximum Ratings” may cause perm anent damage to th e device. This is a stress onl y rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
= 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
TC = 25oC, Unless Otherwise Specified
Ordering Information
PART NUMBER PACKAGE BRAND
HUF75945G3 TO-247 75945G HUF75945P3 TO-220AB 75945P HUF75945S3ST TO-263AB 75945S
NOTE: When ordering, use the entire part number.
HUF75945G3,HUF75945P3,
HUF75945S3ST UNITS
DSS
DGR
GS
D D
DM
D
, T
J
STG
L
pkg
200 V 200 V ±20 V
38 27
Figure 4
310
2.07
-55 to 175
300 260
A A
W
W/oC
o
C
o
C
o
C
©2001 Fairchild Semiconductor Corpo ration HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
HUF75945G3, HUF75945P3, HUF75945S3ST
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage BV Zero Gate Voltage Drain Current I
Gate to Source Leakage Current I
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage V Drain to Source On Resistance r
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case R Thermal Resistance Junction to
Ambient
SWITCHING SPECIFICATIONS (V
GS
= 10V) Turn-On Time t Turn-On Delay Time t Rise Time t Turn-Off Delay Time t Fall Time t Turn-Off Time t
GATE CHARGE SPECIFICATIONS
Total Gate Charge Q Gate Charge at 10V Q Threshold Gate Charge Q Gate to Source Gate Charge Q Gate to Drain “Miller” Charge Q
CAPACITANCE SPECIFICATIONS
Input Capacitance C Output Capacitance C Reverse Transfer Capacitance C
DSSID
DSS
VDS = 190V, VGS = 0V - - 1 µA V
GSS
GS(TH)VGS
DS(ON)ID
θJC
R
θJA
VGS = ±20V - - ±100 nA
TO-247, TO-220, TO-263 - - 0.48oC/W TO-247 - - 30 TO-220, TO-263 - - 62
ON
VDD = 100V, ID = 38A V
d(ON)
d(OFF)
OFF
g(TOT)VGS
g(10)
g(TH)
ISS
OSS
RSS
R (Figures 18, 19)
r
f
VGS = 0V to 10V - 118 153 nC VGS = 0V to 2V - 8 10 nC
gs gd
VDS = 25V, VGS = 0V, f = 1MHz (Figure 12)
= 250µA, VGS = 0V (Figure 11) 200 - - V
= 180V, VGS = 0V, TC = 150oC - - 250 µA
DS
= VDS, ID = 250µA (Figure 10) 2 - 4 V
= 38A, VGS = 10V (Figure 9) - 0.056 0.071 ¾
o o
- - 33 ns
= 10V,
GS GS
= 3.0
-15-ns
-64-ns
-65-ns
- 80 - ns
- - 217 ns
= 0V to 20V VDD = 100V,
= 38A,
I
D
I
= 1.0mA
g(REF)
- 215 280 nC
(Figures 13, 16, 17)
-15-nC
-42-nC
- 4023 - pF
- 880 - pF
- 240 - pF
C/W C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage V
Reverse Recovery Time t Reverse Recovered Charge Q
©2001 Fairchild Semiconductor Corpo ration HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
SD
rr
RR
ISD = 38A - - 1.25 V
= 19A - - 1.00 V
I
SD
ISD = 38A, dISD/dt = 100A/µs - - 281 ns ISD = 38A, dISD/dt = 100A/µs - - 2700 nC
5
5
HUF75945G3, HUF75945P3, HUF75945S3ST
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
POWER DISSIPATION MULTIPLIER
0
150
0255075100 17
125
TC, CASE TEMPERA TURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
40
30
V
= 10V
GS
20
, DRAIN CURRENT (A)
10
D
I
0
25 50 75 100 125 150 17
TC, CASE TEMPERATURE (oC)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
0.1
, NORMALIZED
θJC
Z
THERMAL IMPEDANCE
0.01
-5
10
1000
100
, PEAK CURRENT (A)
TRANSCONDUCTANCE
DM
I
MAY LIMIT CURRENT IN THIS REGION
10
-5
10
VGS = 10V
SINGLE PULSE
NOTES: DUTY FACTOR: D = t
PEAK TJ = PDM x Z
-4
10
-3
10
-2
10
-1
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-4
10
-3
10
-2
10
-1
10
t, PULSE WIDTH (s)
1/t2
x R
+ T
θJC
C
θJC
TC = 25oC FOR TEMPERATURES ABOVE 25 CURRENT AS FOLLOWS:
I = I
25
P
DM
t
1
t
0
10
o
C DERATE PEAK
175 - T
150
0
10
2
1
10
C
1
10
FIGURE 4. PEAK CURRENT CAPAB ILITY
©2001 Fairchild Semiconductor Corpo ration HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
HUF75945G3, HUF75945P3, HUF75945S3ST
Typical Performance Curves
500
100
10
, DRAIN CURRENT (A)
D
I
1
1 10 100
OPERATION IN THIS AREA MAY BE LIMITED BY r
V
DS
DS(ON)
, DRAIN TO SOURCE VOLTAGE (V)
(Continued)
SINGLE PULSE TJ = MAX RATED
T
C
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
75
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX V
= 15V
DD
50
= 25oC
100µs
1ms
10ms
500
200
100
STARTING TJ = 150oC
10
If R = 0
, AVALANCHE CURRENT (A)
tAV = (L)(IAS)/(1.3*RATED BV
AS
I
If R ≠ 0
= (L/R)ln[(IAS*R)/(1.3*RATED BV
t
AV
1
0.001 0.01 0.1 1 tAV, TIME IN AVALANCHE (ms)
STARTING TJ = 25oC
- VDD)
DSS
- VDD) +1]
DSS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
75
VGS = 10V
V
= 5V
GS
50
VGS = 4.5V
10
25
DRAIN CURRENT (A)
D,
I
0
2345
VGS, GATE TO SOURCE VOLTAGE (V)
= 175oC
T
J
T
= -55oC
T
J
= 25oC
J
25
, DRAIN CURRENT (A)
D
I
0
0123456
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX
T
FIGURE 7. TRANSFER CHARACTERISTICS FIGURE 8. SATURATION CHARACTERISTICS
3.5
PULSE DURATION = 80µs
3.0
DUTY CYCLE = 0.5% MAX
2.5
2.0
1.5
ON RESISTANCE
1.0
0.5
NORMALIZED DRAIN TO SOURCE
0
-80 -40 0 40 80 120 200 TJ, JUNCTION TEMPERATURE (oC)
VGS = 10V, ID = 38A
160
1.2
1.0
0.8
NORMALIZED GATE
0.6
THRESHOLD VOLTAGE
0.4
-80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC)
= 25oC
C
VGS = VDS, ID = 250µA
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corpo ration HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
FIGURE 10. NORMALIZED GA TE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
0
HUF75945G3, HUF75945P3, HUF75945S3ST
Typical Performance Curves
1.3 ID = 250µA
1.2
1.1
1.0
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
0.9
-80 -40 0 40 80 120 160 200 T
, JUNCTION TEMPERATURE (oC)
J
(Continued)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
VDD = 100V
8
10000
1000
C
OSS
C, CAPACITANCE (pF)
100
30
0.1 1.0 10 100 200 VDS, DRAIN TO SOURCE VOLTAGE (V)
C
DS
+ C
GD
C
V
RSS
= 0V, f = 1MHz
GS
C
= C
ISS
= C
GD
GS
+ C
GD
FIGURE 12. CAPA C ITANCE vs DRAIN TO SOURCE VOLTAGE
, GATE TO SOURCE VOLTAGE (V)
GS
V
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and W aveforms
TO OBTAIN
VARY t
P
REQUIRED PEAK I
V
GS
AS
R
G
6
4
WAVEFORMS IN
2
0
0 2040608010012
, GATE CHARGE (nC)
Q
g
V
DS
L
+
V
DD
-
DUT
DESCENDING ORDER: ID = 38A
= 10A
I
D
I
AS
BV
DSS
t
P
V
DS
V
DD
0V
P
I
AS
0.01
0
t
AV
t
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
©2001 Fairchild Semiconductor Corpo ration HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
V
I
HUF75945G3, HUF75945P3, HUF75945S3ST
Test Circuits and W aveforms
V
DS
V
GS
I
g(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORMS
V
(Continued)
R
L
DUT
DS
R
L
V
DD
+
V
DD
-
V
GS
0
g(REF)
V
GS
= 2V
Q
g(TH)
Q
gs
Q
V
DS
g(10)
Q
gd
Q
g(TOT)
VGS = 10V
V
= 20
GS
0
t
ON
t
d(ON)
t
V
DS
r
90%
t
d(OFF)
t
OFF
t
f
90%
V
GS
+
V
DD
-
0
10%
DUT
R
GS
V
GS
V
GS
10%
0
50%
PULSE WIDTH
FIGURE 18. SWITCHING TIME TEST CIRCUIT FIGURE 19. SWITCHING TIME WAVEFORM
10%
90%
50%
©2001 Fairchild Semiconductor Corpo ration HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
HUF75945G3, HUF75945P3, HUF75945S3ST
PSPICE Electrical Model
.SUBCKT HUF75945 2 1 3 ; rev 13 October 2000
CA 12 8 6.6e-9 CB 15 14 6.5e-9 CIN 6 8 3.80e-9
DBODY 7 5 DBODYMOD DBREAK 5 11 D B REAK MOD DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 221 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
IT 8 17 1 LDRAIN 2 5 1.0e-9
LGATE 1 9 8.05e-9 LSOURCE 3 7 5.8e-9
GATE
1
MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5.0e-2 RGATE 9 20 0.77 RLDRAIN 2 5 10 RLGATE 1 9 80.5 RLSOURCE 3 7 58 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 1.8e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTE MPMOD 1
S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
LGATE
RLGATE
RGATE
9
CA
-
ESG
+
EVTEMP
+
-
18 22
20
S1A
12
13
8
S1B
EGS EDS
6 8
13
10
RSLC2
6
14 13
+
+
6 8
-
-
DPLCAP
EVTHRES
+
19
8
S2A
S2B
15
CB
CIN
-
+
5 8
-
5
RSLC1
51
+
5
51
-
50 RDRAIN
21
MSTRO
14
ESLC
16
8
MMED
DBREAK
11
EBREAK
MWEAK
RSOURCE
RBREAK
17 18
IT
8
RVTHRES
LDRAIN
RLDRAIN
+
17 18
DBODY
DRAIN
2
-
LSOURCE
7
RLSOURCE
RVTEMP 19
SOURCE
3
-
VBAT
+
22
ESLC 51 50 VALUE={(V (5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),2.5))} .MODEL DBODYMOD D (IS = 2.8e-12 RS = 3.0e-3 XTI = 5.5 TRS1 = 3.5e-3 TRS2 = 1e-5 CJO = 2.55e-9 TT = 1.52e-7 M = 0.42)
.MODEL DBREAKMOD D (RS = 1.2e- 0TRS1 = 1e- 3TRS2 = 1e-6) .MODEL DPLCAPMOD D (CJ O = 4.6e - 9IS = 1e-30 N = 10 M = 0.9) .MODEL MMEDMO D N MOS (VTO = 3.05 K P = 2.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.77) .MODEL MSTR OMOD NMOS (VTO = 3.55 KP = 100 IS = 1e-3 0 N = 1 0 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.69 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7.70 ) .MODEL RBREAKMOD RES (TC1 =1.27e- 3TC2 = 1.0e-6) .MODEL RDRAINMOD RES (TC1 = 9.90e-3 TC2 = 3.60e-5) .MODEL RSLCMOD RES (TC1 = 3.0e-3 TC2 = 1.0e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6) .MODEL RVTHRESMOD RES (TC1 = -2.90e-3 TC2 = -1.10e-5) .MODEL RVTEMPMOD RES (TC1 = -2.80e- 3TC2 = 1.70e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.5 VOFF= -4.5) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.5 VOFF= -5.5) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.4) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VO N = 0.4 VOFF= -0.3)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corpo ration HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
HUF75945G3, HUF75945P3, HUF75945S3ST
SABER Electrical Model
REV 13 October 2000 template huf75945 n2,n1,n3
electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl = 2.8e-12, rs = 3.0e-3, xti = 5.5, trs1 = 3.5e-3, trs2 = 1.0e-5, cjo = 2.55e -9, tt = 1.52e-7, m = 0.42) dp..model dbreakmod = (rs = 1.2, trs1 = 1.0e-3, trs2 = 1.0e-6) dp..model dplcapmod = (cjo = 4.6e-9, isl = 10e-30, nl=10, m = 0.9) m..model mmedmod = (type=_n, vto = 3.05, kp = 2.5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.55, kp = 100, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.69, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -5.5, voff = -4.5) sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -4.5, voff = -5.5) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.4) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.4, voff = -0.3)
c.ca n12 n8 = 6.6e-9 c.cb n15 n14 = 6.5e-9 c.cin n6 n8 = 3.8e-9
dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod
i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 8.05e-9 l.lsource n3 n7 = 5.80e-9
GATE
LGATE
1
RLGATE
RGATE
9
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.27e-3, tc2 = 1.00e-6 res.rdrain n50 n16 = 5.0e-2, tc1 = 9.9e-3, tc2 =3.6e-5
12
res.rgate n9 n20 = 0.77 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 80.5 res.rlsource n3 n7 = 58 res.rslc1 n5 n51= 1e-6, tc1 = 3e-3, tc2 = -1.0e-6
CA
res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 1.8e-3, tc1 = 1.0e-3, tc2 =1e-6 res.rvtemp n18 n19 = 1, tc1 = -2.8e-3, tc2 = 1.70e-6 res.rvthres n22 n 8 = 1, tc1 = -2.9e-3, tc2 = 1.1e-5
spe.ebreak n11 n7 n17 n18 = 221 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc =1
ESG
EVTEMP +
18 22
20
S1A
13
S1B
EGS EDS
DPLCAP
10
RSLC2
-
6 8
EVTHRES
+
+
6
-
S2A
14 13
8
S2B
13
+
+
6 8
-
-
5
RSLC1
51
ISCL
MMED
DBREAK
MWEAK
EBREAK
RSOURCE
RBREAK
17 18
IT
8
RVTHRES
50 RDRAIN
16
21
-
19
8
MSTRO
CIN
15
CB
8
14
+
5 8
-
LDRAIN
RLDRAIN
11
+
17 18
-
7
RLSOURCE
RVTEMP 19
-
+
22
DBODY
LSOURCE
VBAT
DRAIN
2
SOURCE
3
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6*100))** 2.5)) } }
©2001 Fairchild Semiconductor Corpo ration HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
SPICE Thermal Model
REV 13 October 2000
HUF75945T
CTHERM1 th 6 6.45e-3 CTHERM2 6 5 3.00e-2 CTHERM3 5 4 1.40e-2 CTHERM4 4 3 1.65e-2 CTHERM5 3 2 4.85e-2 CTHERM6 2 tl 1.00e-1
RTHERM1 th 6 3.24e-3 RTHERM2 6 5 8.08e-3 RTHERM3 5 4 2.28e-2 RTHERM4 4 3 1.00e-1 RTHERM5 3 2 1.10e-1 RTHERM6 2 tl 1.40e-1
HUF75945G3, HUF75945P3, HUF75945S3ST
RTHERM1
RTHERM2
JUNCTION
th
CTHERM1
6
CTHERM2
5
SABER Thermal Model
SABER thermal model HUF75945T template thermal_model th tl
thermal_c th, tl { ctherm.ctherm1 th 6 = 6.45e-3 ctherm.ctherm2 6 5 = 3.00e-2 ctherm.ctherm3 5 4 = 1.40e-2 ctherm.ctherm4 4 3 = 1.65e-2 ctherm.ctherm5 3 2 = 4.85e-2 ctherm.ctherm6 2 tl = 1.00e-1
rtherm.rtherm1 th 6 = 3.24e-3 rtherm.rtherm2 6 5 = 8.08e-3 rtherm.rtherm3 5 4 = 2.28e-2 rtherm.rtherm4 4 3 = 1.00e-1 rtherm.rtherm5 3 2 = 1.10e-1 rtherm.rtherm6 2 tl = 1.40e-1 }
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM3
4
CTHERM4
3
CTHERM5
2
CTHERM6
tl
CASE
©2001 Fairchild Semiconductor Corpo ration HUF75945G3, HUF75945P3, HUF75945S3ST Rev. B
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Advance Information
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No Identification Needed
Formative or In Design
First Production
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effectiveness.
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Rev. H4
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