Fairchild HCPL-3700 User Manual

tm

C

R

C

00

G

1

G

2

HCPL-3700 AC/DC to Logic Interface Optocoupler

April 2007

HCPL-3700
AC/DC to Logic Interface Optocoupler

Features

AC or DC input

■

■

Programmable sense voltage
Logic level compatibility

■

■

Threshold guaranteed over temperature (0°C to 70°C)

■

Optoplanar™ construction for high common mode
immunity

■

UL recognized (file # E90700)
VDE certified – ordering option ‘V’, e.g., HCPL3700V

■

Description

The HCPL-3700 voltage/current threshold detection
optocoupler consists of an AlGaAs LED connected to a
threshold sensing input buffer IC which are optically cou­pled to a high gain darlington output. The input buffer
chip is capable of controlling threshold levels over a wide
range of input voltages with a single resistor. The output
is TTL and CMOS compatible.

Applications

■

Low voltage detection
5 V to 240 V AC/DC voltage sensing

■

■

Relay contact monitor

■

Current sensing
Microprocessor Interface

■

■

Industrial controls

Schematic Package

AC

DC+

DC-

1

2

3

8

V

CC

7

NC

6

V

O

8

1

45

AC GND

8

1

8

1

TRUTH TABLE

(Positive Logic)

Input Output

HL

LH

A 0.1 µF bypass capacitor must
be connected between pins 8

AC/D

POWE

ND

HCPL-37

LOGI

ND

and 5.

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
HCPL-3700 Rev. 1.0.1

Absolute Maximum Ratings

(No derating required up to 70°C)

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol Parameter Value Units

T

STG

T

OPR

T

SOL

EMITTER

I

IN

V

IN

P

IN

P

T

DETECTOR

I

O

V

CC

V

O

P

O

Storage Temperature -55 to +125 °C

Operating Temperature -40 to +85 °C

Lead Solder Temperature 260 for 10 sec °C

Input Current Average 50 (Max.) mA

Surge, 3ms, 120Hz Pulse Rate 140 (Max.)

Tr ansient, 10µs, 120Hz Pulse Rate 500 (Max.)

Input Voltage (Pins 2-3) -0.5 (Max.) V

Input Power Dissipation

Total Package Power Dissipation

Output Current (Average)

(1)

(3)

(2)

230 (Max.) mW

305 (Max.) mW

30 (Max.) mA

Supply Voltage (Pins 8-5) -0.5 to 20 V

Output Voltage (Pins 6-5) -0.5 to 20 V

Output Power Dissipation

(4)

210 (Max.) mW

HCPL-3700 AC/DC to Logic Interface Optocoupler

Notes:

1. Derate linearly above 70°C free-air temperature at a rate of 1.8 mW/°C.

2. Derate linearly above 70°C free-air temperature at a rate of 2.5 mW/°C.

3. Derate linearly above 70°C free-air temperature at a rate of 0.6 mA/°C.

4. Derate linearly above 70°C free-air temperature at a rate of 1.9 mW/°C.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Min. Max. Units

V

CC

T

A

f Operating Frequency 0 4 kHz

Supply Voltage 2 18 V

Operating Temperature 0 70 °C

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
HCPL-3700 Rev. 1.0.1 2

≥

≤

≥

≥

≥

≥

≤

HCPL-3700 AC/DC to Logic Interface Optocoupler

Electrical Characteristics

(T

= 0°C to 70°C Unless otherwise specified)

A

Symbol Parameter Test Conditions Min. Typ. Max. Unit

V

V

V

V

V

V

V

V

I

TH+

I

TH-

V

V

I

HYS

HYS

IHC1

IHC2

IHC3

V

I

D1,2

D3,4

V

I

OH

I

CCL

I

CCH

C

TH+

TH+

Input Threshold Current V

Input Threshold
Voltage

TH-

TH-

Hysteresis I

Input Clamp Voltage V

DC
(Pins 2,3)

AC
(Pins 1,4)

= V

IN

V

= 0.4 V, I

O

V

= V

IN

V

= 4.5 V, V

CC

I

4.2mA

O

V

= V

IN

V

= 4.5 V, V

CC

I

100µA

O

|V

= V

IN

V

= 4.5 V, V

CC

I

4.2 mA

O

|V

= |V

IN

V

= 4.5 V, V

CC

I

100µA

O

= I

HYS

V

= V

HYS

= V

IHC1

I

= 10 mA,

IN

, V

TH+

– V

2

- V

2

1

TH+

= 4.5 V 1.96 2.4 3.11 mA

CC

4.2mA

O

(Pins 1 & 4 Open)

3

= 0.4V

O

(Pins 1 & 4 Open)

3

= 2.4 V

O

– V

| (Pins 2 & 3 Open)

4

= 0.4 V

O

- V

| (Pins 2 & 3 Open)

1

4

= 2.4 V

O

– I

TH-

– V

TH+

2

- V

TH-

, V

3

3

(5)

(5)

(5)

(5)

(5)

= GND

1.00 1.2 1.62 mA

3.35 3.8 4.05 V

2.01 2.5 2.86 V

4.23 5.0 5.50 V

2.87 3.7 4.20 V

1.2 mA

1.3 V

5.4 6.3 6.6 V

Pins 1 & 4 connected to Pin 3

V

= |V

– V

|, |I

IHC2

4

| = 10mA

IN

1

6.1 7.0 7.3 V

(Pins 2 & 3 Open)

V

IHC3

I

= 15mA (Pins 1 & 4 Open)

IN

ILC

Input Current VIN = V2 – V3 = 5.0V

IN

V

ILC

I

= -10mA

IN

– V3, V3 = GND,

= V

2

= V2 – V3, V3 = GND,

12.5 13.4 V

-0.75 V

3.0 3.7 4.4 mA

(Pins 1 & 4 Open)

Bridge Diode
Forward Voltage

Logic LOW Output Voltage VCC = 4.5 V, IOL = 4.2mA

OL

Logic HIGH Output Current VOH = VCC = 18V

Logic LOW Supply Current V2 – V3 = 5.0V, VO = Open,

IIN = 3mA 0.65 V

IIN = 3mA 0.65 V

(5)

(5)

0.04 0.4 V

1.0 4 mA

V

= 5V

CC

Logic HIGH Supply Current VCC = 18V, VO = Open 0.01 4 µA

Input Capacitance f = 1MHz, VIN = 0V

IN

50 pF

(Pins 2 & 3, Pins 1 & 4 Open)

100 µA

Note:

5. Logic LOW output level at pin 6 occurs when V
Logic HIGH output level at pin 6 occurs when V

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
HCPL-3700 Rev. 1.0.1 3

IN

IN

V

TH+

V

TH-

and when V
and when V

IN

IN

> V
< V

TH-

TH+

once V

once V

exceeds V

IN

decreases below V

IN

TH+

.

.

TH-

HCPL-3700 AC/DC to Logic Interface Optocoupler

Switching Characteristics (T

= 25°C, VCC = 5 V Unless otherwise specified)

A

Symbol AC Characteristics Test Conditions Min. Typ. Max. Unit

T

PHL

Propagation Delay Time
(to Output Low Level)

T

PLH

Propagation Delay Time
(to Output High Level)

Output Rise Time (10–90%) RL = 4.7kΩ, CL = 30pF 45 µs

t

r

Output Fall Time (90–10%) RL = 4.7kΩ, CL = 30pF 0.5 µs

t

f

| Common Mode Transient

|CM

H

Immunity (at Output High Level)

| Common Mode Transient

|CM

L

Immunity (at Output Low Level)

Package Characteristics

RL = 4.7kΩ, CL = 30pF

RL = 4.7kΩ, CL = 30pF

IIN = 0 mA, RL = 4.7kΩ,
V

= 2.0 V, VCM = 1400V

O min

IN = 3.11mA, RL = 4.7kΩ,
V

= 0.8V, VCM = 140V

O max

(TA = 0°C to 70°C Unless otherwise specified)

(6)

(6)

(7)(8)

(7)(8)

6.0 15 µs

25.0 40 µs

4000 V/µs

600 V/µs

Symbol Characteristics Test Conditions Min. Typ. Max. Unit

V

ISO

R

I-O

C

I-O

Withstand Insulation Voltage Relative humidity < 50%,

T

= 25°C, t = 1 min,

A

I

I-O

Resistance (input to output) VIO = 500Vdc

≤ 2µA

(9)(10)

(9)

2500 V

12

10

Capacitance (input to output) f = 1MHz, VIO = 0Vdc 0.6 pF

RMS

Ω

Notes:

6. T

propagation delay is measured from the 2.5V level of the leading edge of a 5.0V input pulse (1µs rise time) to

PHL

the 1.5 V level on the leading edge of the output pulse. T

propagation delay is measured on the trailing edges

PLH

of the input and output pulse. (Refer to Fig. 9)

7. Common mode transient immunity in logic high level is the maximum tolerable (positive) dV

edge of the common mode pulse signal V

, to assure that the output will remain in a logic high state (i.e., VO >

CM

2.0 V). Common mode transient immunity in logic low level is the maximum tolerable (negative) dV
trailing edge of the common mode pulse signal, V
(i.e., V

8. In applications where dV

< 0.8 V). Refer to Fig. 10.

O

cm

/dt may exceed 50,000 V/µs (Such as static discharge), a series resistor, RCC,

, to assure that the output will remain in a logic low state

CM

/dt on the leading

cm

/dt on the

cm

should be included to protect the detector chip from destructive surge currents. The recommended value for
R

is 240V per volt of allowable drop in VCC (between pin 8 and VCC) with a minimum value of 240Ω.

CC

9. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are

shorted together.

10. The 2500 V

/1 min. capability is validated by a 3.0 kV

RMS

11. AC voltage is instantaneous voltage for V

12. All typicals at T

= 25°C, VCC = 5V unless otherwise specified.

A

TH+

& V

TH-

.

/1 sec. dielectric voltage withstand test.

RMS

©2005 Fairchild Semiconductor Corporation www.fairchildsemi.com
HCPL-3700 Rev. 1.0.1 4