Fairchild FSD210, FSD200 Operator's Manual

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Page 1

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Rev.1.0.3

Features

• Single Chip 700V Sense FET Power Switch

• Precision Fixed Operating Frequency (134kHz)

• Advanced Burst-Mode operation Consumes under 0.1W at 265Vac and no load (FSD210 only)

• Internal Start-up Switch and Soft Start

• Under Voltage Lock Out (UVLO) with Hysteresis

• Pulse by Pulse Current Limit

• Over Load Protection (OLP)

• Internal Thermal Shutdown Function (TSD)

• Auto-Restart Mode

• Frequency Modulation for EMI

• FSD200 does not require an auxiliary bias winding

Applications

• Charger & Adaptor for Mobile Phone, PDA & MP3

• Auxiliary Power for White Goods, PC, C-TV & Monitor

Description

The FSD200 and FSD210 are integrated Pulse Width Modulators (PWM) and Sense FETs specially designed for high performance off-l ine Switch Mode Power Supplies (SMP S) with minimal external components. Both devices are monolithic high voltage power switching regulators which combine an LDMOS Sense FET with a voltage mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency modulatio n for reduced EMI, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), optimized gate turn-on/turn off driver, thermal shut down protection (TSD), temperature compensated precision current sources for loop compe nsation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSD200 and FSD210 reduce total component count, design size, weight and at the same time increase efficiency, productivity, and system reliability. The FSD200 eliminates the need for an auxiliary bi as winding at a small cost of increased supply power. Both devices are a basic platform well suited for cost effective designs of flyback converters.

Table 1. Notes: 1. Typical continuous power in a non-ventilated enclosed adapt er me as ured at 50°C ambient. 2. Maximum practical continuous power in an open frame design at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler.

Typical Circuit

Figure 1. Typical Flyback Application using FSD210

Figure 2. Typical Flyback Application using FSD200

OUTPUT POWER TABLE

PRODUCT

230VAC ±15%

(3)

85-265VAC

Adapter

(1)

Open

Frame

(2)

Adapter

(1)

Open

Frame

(2)

FSD210 5W 7W 4W 5W

FSD200 5W 7W 4W 5W FSD210M5W7W4W5W FSD200M5W7W4W5W

Drain

Source

Vstr

Vfb Vcc

PWM

OUT

Drain

Source

Vstr

Vfb Vcc

PWM

OUT

FSD210, FSD200

Green Mode Fairchild Power Switch (FPS

)

Page 2

FSD210, FSD200

Internal Block Diagram

Figure 3. Functional Block Diagram of FSD210

Figure 4. Functional Block Diagram of FSD200 show in g internal high voltage regulato r

UVLO

Voltage

Ref

Vstr

Vcc

Internal

Bias

Rsense

Iover

S/S

3mS

1, 2, 3

OSC

SRQ

TSD

SRQ

LEB

OLP

Reset

A/R

DRIVER

Frequency Modulation

5uA

250uA

Vck

Vth

SFET

Drain

GND

Vfb

BURST

8.7/6.7V

Rsense

Iover

S/S

3mS

1, 2, 3

OSC

SRQ

TSD

SRQ

LEB

OLP

Reset

A/R

DRIVER

Frequency Modulation

5uA

250uA

Vck

Vth

SFET

Drain

GND

Vfb

BURST

UVLO

Voltage

Ref.

HV/REG

INTERNAL

BIAS

ON/OFF

Vstr

Vcc

Page 3

FSD210, FSD200

Pin Definitions

Pin Configuration

Figure 5. Pin Configuration (Top View)

Pin Number Pin Name Pin Function Description

1, 2, 3 GND Sense FET source terminal on primary side and internal control ground.

4Vfb

The feedback voltage pin is the inverting input to the PWM comparator with nominal input levels between 0.5Vand 2.5V. It has a 0.25mA current source connected internally while a capacitor and opto coupler are typically connected externally. A feedback voltage of 4V triggers overload protection (OLP). There is a time delay while charging between 3V and 4V using an internal 5uA current source, which prevents false triggering under transient conditions but still allows the protection mechanism to operate under true overload conditions.

5Vcc

FSD210

Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 8 (Vstr) via an internal switch during startup (see Internal Block Diagram section). It is not until Vcc reaches the UVLO upper threshold (8.7V) that the internal start-up switch opens and device power is supplied via the auxiliary transformer winding.

FSD200

This pin is connected to a storage capacitor. A high voltage regulator connected between pin 8 (Vstr) and this pin, provides the supply voltage to the FSD200 at startup and when switching during normal operation. The FSD200 eliminates the need for auxiliary bias winding and associated external components.

7Drain

The Drain pin is designed to connect directly to the primary lead of the transformer and is capable of switching a maximum of 700V. Minimizing the length of the trace connecting this pin to the transformer will decrease leakage inductance.

8Vstr

The startup pin connects directly to the rectified AC line voltage source for both the FSD200 and FSD210. For the FSD210, at start up the internal switch supplies internal bias and charges an external storage capacitor placed between the Vcc pin and ground. Once this reaches 8.7V, the internal current source is disabled. For the FSD200, an internal high voltage regulator provides a constant supply voltage.

1 2

3 45

GND GND GND

Vfb

Vstr

Drain

Vcc

7-DIP 7-LSOP

Page 4

FSD210, FSD200

Absolute Maximum Ratings

(Ta=25°C unless otherwise specified)

Thermal Impedance

Note:

1. Free standing without heat sink.

2. Measured on the GND pin close to plastic interface.

3. Soldered to 100mm

copper clad.

4. Soldered to 300mm

copper clad.

Parameter Symbol Value Unit

Maximum Supply Voltage (FSD200) V

CC,MAX

10 V

Maximum Supply Voltage (FSD210) V

CC,MAX

20 V

Input Voltage Range V

−0.3 to V

STOP

Operating Junction Temperature. T

+150 °C

Operating Ambient Temperature T

−25 to +85 °C

Storage Temperature Range T

STG

−55 to +150 °C

Parameter Symbol Value Unit 7DIP

Junction-to-Ambient Thermal

(1)

74.07

(3)

°C/W

(1)

60.44

(4)

°C/W

Junction-to-Case Thermal

(2)

22.00 °C/W

7LSOP

Junction-to-Ambient Thermal

(1)

- °C/W

(1)

- °C/W

Junction-to-Case Thermal

(2)

- °C/W

Page 5

FSD210, FSD200

Electrical Characteristics

(Ta=25°C unless otherwise specified)

Note:

1. These parameters, although guaranteed, are not 100% tested in production

2. This para meter is derived from characterization

Parameter Symbol Condition Min. Typ. Max. Unit Sense FET SECTION

Drain-Source Breakdown Voltage BV

DSS

= 0V, ID = 100µA 700 - - V

Startup Voltage (Vstr) Breakdown BV

STR

700 - - V

Off-State Current I

DSS

= 560V - - 100 µA

On-State Resistance R

DS(ON)

Tj = 25°C, ID = 25mA - 28 32 Ω Tj = 100°C, I

= 25mA - 42 48 Ω

Rise Time T

= 325V, ID = 50mA - 100 - ns

Fall Time T

= 325V, lD = 25mA - 50 - ns

CONTROL SECTION

Output Frequency F

OSC

Tj = 25°C 126 134 142 kHz

Output Frequency Modulation F

MOD

Tj = 25°C-±4-kHz

Feedback Source Current I

Vfb = 0V 0.22 0.25 0.28 mA

Maximum Duty Cycle D

MAX

Vfb = 3.5V 60 65 70 %

Minimum Duty Cycle D

MIN

Vfb = 0V 0 0 0 %

UVLO Threshold Voltage (FSD200)

START

6.377.7V

STOP

After turn on 5.3 6 6.7 V

UVLO Threshold Voltage (FSD210)

START

8.0 8.7 9.4 V

STOP

After turn on 6.0 6.7 7.4 V

Supply Shunt Regulator (FSD200) V

CCREG

--7-V

Internal Soft Start Time T

S/S

-3-ms

BURST MODE SECTION

Burst Mode Voltage

BURH

Tj = 25°C

0.58 0.64 0.7 V

BURL

0.5 0.58 0.64 V

Hysteresis - 60 - mV

PROTECTION SECTION

Drain to Source Peak Current Limit I

OVER

0.275 0.320 0.365 A

Current Limit Delay

(1)

CLD

Tj = 25°C - 220 - ns

Thermal Shutdown Temperature (Tj)

(1)

125 145 160 °C

Shutdown Feedback Voltage V

- 3.5 4.0 4.5 V

Feedback Shutdown Delay Current I

DELAY

Vfb = 4.0V 3 5 7 µA

Leading Edge Blanking Time

(2)

LEB

200 - - ns

TOTAL DEVICE SECTION

Operating Supply Current (FSD200) I

Vcc = 7V - 600 - µA

Operating Supply Current (FSD210) I

Vcc = 11V - 700 - µA

Start Up Current (FSD200) I

START

Vcc = 0V - 1 1.2 mA

Start Up Current (FSD210) I

START

Vcc = 0V - 700 900 µA

Vstr Supply Voltage Vcc = 0V 20 - - V

Page 6

FSD210, FSD200

Comparison Between FSDH565 and FSD210

Function FSDH0565 FSD210 FSD210 Advantages

Soft-Start not applicable 3mS • Gradually increasing current limit

during soft-start further reduces peak current and voltage component stresses

• Eliminates external components used for soft-start in most applications

• Reduces or eliminates output overshoot

Switching Frequency 100kHz 134kHz • Smaller transformer Frequency Modulation not applicable ±4kHz • Reduced conducted EMI Burst Mode Operation not applicable Yes-built into

controller

• Improve light load efficiency

• Reduces no-load consumption

• Transformer audible noise reduction

Drain Creepage at Package

1.02mm 3.56mm DIP

3.56mm LSOP

• Greater immunity to acting as a result of build-up of dust, debris and other contaminants

Page 7

FSD210, FSD200

Typical Performance Characteristics

(These characteristic graphs are normalized at Ta=25℃)

Frequency vs. Temp Operating Current vs. Temp

Peak Current Limit vs. Temp Feedback Source Current vs. Temp

Vstop Voltage vs. Temp

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Feedback SOurce Current (A)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Peak Current Limit (A)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Operating Current (A)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Fosc (kHz)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-25 0 25 50 75 100 125

Junction Temperature (℃)

Vstart (V)

0.00

0.20

0.40

0.60

0.80

1.00

1.20

-25 0 25 50 75 100 125

Junction Temperature (℃)

Vstop (V)

Vstart Voltage vs. Temp

Page 8

FSD210, FSD200

Typical Performance Characteristics

(Continued)

(These characteristic graphs are normalized at Ta=25℃)

On State Resistance vs. Temp

Breakdown Voltage vs. Temp

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Vcc Regulation Voltage (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

-25 0 25 50 75 100 125 Junction Temperature (℃)

On State Resistance (Ω)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125 Junction Temperature (℃)

BVdss (V)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

VSD (V)

Vcc Regulation Voltage vs. Temp (for FSD200) Shutdown Feedback Voltage vs. Temp

Start Up Current vs. Temp (for FSD210)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

-25 0 25 50 75 100 125

Junction Temperature (℃)

Istart (A)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

-25 0 25 50 75 100 125

Junction Temperature (℃)

Istart (A)

Start Up Current vs. Temp (for FSD200)

Page 9

FSD210, FSD200

Functional Description

1. Startup : At startup, the internal high voltage current source supplies the internal bias and charges the external Vcc capacitor as shown in figure 7. In the case of the FSD210, when Vcc reaches 8.7V the device starts switching and the internal high voltage current source is disabled (see figure 1). The device continues to switch provided that Vcc does not drop below 6.7V. For FSD210, after startup, the bias is supplied from the auxiliary transformer winding. In the case of FSD200, Vcc is continuously supplied from the external high voltage source and Vcc is regulated to 7V by an internal high voltage regulator (HVReg), thus eliminating the need for an auxiliary winding (see figure 2).

Figure 6. Internal startup circuit

Calculating the Vcc capacitor is an important step to designing in the FSD200/210. At initial start-up in both the FSD200/210, the stand-by maximum current is 100uA, supplying current to UVLO and Vref Block. The charging current (i) of the Vcc capacitor is equal to Istr - 100uA. After Vcc reaches the UVLO start voltage only the bias winding supplies Vcc current to device. When the bias winding voltage is not sufficient, the Vcc level decreases to the UVLO stop voltage. At this time Vcc oscillates. In order to prevent this ripple it is recommended that the Vcc capacitor be sized between 10uF and 47uF.

2. Feedback Control : The FSD200/210 are both voltage mode devices as shown in Figure 8. Usually, a H11A817 optocoupler and KA431 voltage reference (or a FOD2741 integrated optocoupler and voltage reference) are used to implement the isolated secondary feedback network. The feedback voltage is compared with an internally generated sawtooth waveform, directly controlling the duty cycle. When the KA431 reference pin voltage exceeds the internal reference voltage of 2.5V, the optocoupler LED current increases pulling down the feedback voltage and reducing the duty cycle. This event will occur when either the input voltage increases or the output load decreases.

Figure 7. Charging the Vcc c apacitor through Vstr

3. Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET , caused by the primary side capacitance and secondary side rectifier diode reverse recovery. Exceeding the pulse-by-pulse current limit could cause premature termination of the switching pulse (see Protection Section). To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the over current comparator for a short time (TLEB) after the Sense FET is turned on.

Figure 8. PWM and feedback circuit

4. Protection Circuit : The FSD200/210 has 2 self protection functions: over load protection (OLP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC with no external components, system

Vin,dc

Vstr

Vcc

Reg.

Vin,dc

Vstr

Vcc

Istr Istr

FSD210 FSD200

8.7V/

6.7V

Vin,dc

Vin,dcVin,dc

Vin,dc

Vstr

VstrVstr

Vstr

Istr

IstrIstr

Istr

J-FET

J-FETJ-FET

J-FET

UVLO

Vref

max

max max

max

100uA

100uA100uA

100uA

i = Istr-max

i = Istr-max i = Istr-max

i = Istr-max

1 00uA

1 00uA1 00uA

1 00uA

i = Istr-max 1 00uA

i = Istr-max 1 00uAi = Istr-max 1 00uA

i = Istr-max 1 00uA

FSD2xx

FSD2xxFSD2xx

FSD2xx

Vcc

VccVcc

Vcc

UVLO

start

UVLO

stop

Vcc

Vcc must not drop

to UVLO stop

Auxiliary winding

voltage

OSC

Vcc

Vref

5uA 0.25mA

Gate

driver

OLP

Vfb

KA431

Cfb

Page 10

FSD210, FSD200

reliability is improved without a cost increase. If either of these thresholds are triggered, the FPS starts an auto-restart cycle. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage (6.7V:FSD210, 6V:FSD200), the protection is reset and the internal high voltage current source charges the Vcc capacitor. When Vcc reaches the UVLO start voltage (8.7V:FSD210,7V:FSD200), the device attempts to resume normal operation. If the fault condition is no longer present start up will be successful. If it is still present the cycle is repeated (see figure 10).

Figure 9. Protection bloc k

4.1 Over Load Protection (OLP) : Over load protection occurs when the load current exceeds a pre-set level due to an abnormal situation. If this occurs, the protection circuit should be triggered to protect the SMPS. It is possible that a short term load transient can occur under normal operation. In order to avoid false shutdowns, the over load protection circuit is designed to trigger after a delay. Therefore the device can differentiate between transient over loads and true fault conditions. The maximum input power is limited using the pulse-by-pulse current limit feature. If the load tries to

draw more than this, the output voltage will drop below its set value. This reduces the optocoupler LED current which in turn reduces the photo-transistor current (see figure 9). Therefore, the 250uA current source will charge the feedback pin capacitor, Cfb, and the feedback voltage, Vfb, will increase. The input to the feedback comparator is clamped at 3V. Once Vfb reaches 3V, the device switches at maximum power, the 250uA current source is blocked and the 5uA source continues to charge Cfb. Once Vfb reaches 4V, switching stops.and overload protection is triggered. The resultant shutdown delay time is set by the time required to charge Cfb from 3Vto 4Vwith 5uA as shown in Fig. 10.

4.2 Thermal Shutdown (TSD) : The Sense FET and the control IC are integrated, making it easier for the control IC

to detect the temperature of the Sense FET. When the temperature exceeds approximately 145°C, thermal shutdown is activated.

Figure 10. Over load protection delay

5. Soft Start : FSD200/210 has an internal soft start circuit that gradually increases current through the Sense FET as shown in figure 11. The soft start time is 3msec in FSD200/

210.

Figure 11. Internal Soft Start

6. Burst operation : In order to minimize the power dissipation in standby mode, the FSD200/210 implements burst mode functionality (see figure 12). As the load decreases, the feedback voltage decreases. As shown in figure 13, the device automatically enters burst mode when the feedback voltage drops below V

BURL

(0.58V). At this point switching stops and the output voltages start to drop at a rate dependant on standby current load. This causes the feedback voltage to rise. Once it passes V

BURH

(0.64V) switching starts again. The feedback voltage falls and the process repeats. Burst mode operation alternately enables and disables switching of the power Sense FET thereby reducing switching loss in

OSC

Vfb

SRQ

GATE

DRIVER

FSD2xx

OLP, TSD

Protection Block

5uA 250uA

RESET

Vth 4V

OLP

TSD

SRQ

A/R

Cfb

3VR

Vfb

OLP

t1 t3

t1<<t2, t3 t1 = -1/RC Χ

Χ Χ

Χ ln( 1-v(t1)/R ) v(t1)=3V

t2 = Cfb Χ

Χ Χ

Χ {v(t1+t2)-v(t1)} /

/ /

/ Idelay

FPS Switching Area

Idelay (5uA) charges Cfb

IC Reset

under Vstop of UVLO

0.2A

0.25A

0.3A

3mS

Iover

FSD200/210

I(A)

Page 11

FSD210, FSD200

standby mode.

Figure 12. Circuit for burst operation

Figure 13. Burst mode oper ation

7. Frequency Modulation : EMI reduction can be accomplished by modulating the switching frequency of a SMPS. Frequency modulation can re duce EMI by spreading the energy over a wider frequency range. The amount of EMI reduction is directly related to the level of modulation (Fmod) and the rate of modulation. As can be seen in Figure 14, the frequency changes from 130kHz to 138kHz in 4mS for the FSD200/FSD210. Frequency modulation allows the use of a cost effective inductor instead of an AC input mode choke to satisfy the requirements of world wide EMI limits.

Figure 14. Frequency Modu l ation Waveforms

Figure 15. FSDH0165 Full Range EMI scan(100kHz, no

Frequency Modulation) with charger set

Figure 16. FSD210 Full Range EMI scan(134kHz, with Fre-

quency Modulation) with charger set

OSC

Vfb

SRQ

GATE

DRIVER

5uA 250uA

0.64V /0.58V

on/off

FSD2xx

Burst Operation Block

Vds

0.58V

0.64V

Ids

set

time

138kHz

134kHz

130kHz

8kHz

Turn-on

Turn-off

point

Internal

Oscillator

Drain to Source voltage

Vds

Waveform

Drain to Source current

Frequency(MHz)

Amplitude(dBµV)

CISPR22Q(PK) CISPR22A(AV)

Amplitude(dBµV)

Frequency(MHz)

CISPR22Q(PK) CISPR22A(AV)

Page 12

FSD210, FSD200

Typical application circuit

Features

• High efficiency (>67% at Universal Input)

• Low zero load power consumption (<100mW at 240Vac) with FSD210

• Low component count

• Enhanced system reliability through various protection functions

• Internal soft-start (3ms)

• Frequency Modulation for low EMI

Key Design Notes

• The constant voltage (CV) mode control is implemented with resistors, R8, R9, R10 and R11, shunt regulator, U2, feedback capacitor, C9 and opto-coupler, U3.

• The constant curren t (CC ) mode con tro l is desi gned w ith res istor s, R8, R9, R1 5, R16, R17 and R19, NPN tra nsisto r, Q1 and NTC, TH1. When the volta ge across cur rent sensin g resis tors, R15,R1 6 and R17 is 0. 7V, the NPN transistor turns on and the current through the opto coupler LED increases. This reduces the feedback voltage and duty ratio. Theref or e, the output voltage decreases and the output current is regulated.

• The NTC(negative thermal coefficient) is used to compensate the temperature characteristics of the transistor Q1.

1. Schematic

Application Output power Input voltage Output voltage (Max current)

Cellular Phone Charger 3.38W Universal input (85-265Vac) 5.2V (650mA)

For FSD21x

For FSD21xFor FSD21x

For FSD21x

4uH

C8 330uF 16V

L1 330uH

R19 510R

510R

1N4148

R3 47k

TH1

10k

R15 3R0

39R

KSP2222A

U2 TL431

1N4007

R16 3R0

C9 470nF

TX1

R10

2.2k

4.7uF 400V

100nF

H11A817B

R1 4.7k

4.7UF 400V

C5 33uF 50V

Fuse

1W, 10R

C6 152M-Y, 250Vac

1N4007

H11A817B

4.7M, 1/4W

R17 3R0

1N4007

R9 56R

UF4007

R12 2k

C7 330uF 16V

(5.2V/0.65A)

47k

C10

4.7uF 50V

FSD210

142

Vstr

Vcc

Drain

GND

Vfb

GND

SB260

4.7M 1/4W

102k 1kV

Page 13

FSD210, FSD200

2. Demo Circuit Part List

3. Transformer Schematic Diagram

4. Winding Specification

5. Electrical Characteristics

TO-92 Type, LM431Vref=2.495V(Typ.)1KA431AZU2

Iover=0.3A, Fairchildsemi0.5A/700V1FSD210

(FSD200)

-CTR 80~160%1H11A817AU3

DO41 Type1A/1000V Ultra Fast Diode1UF4007D5 D0-213 Type10mA/100V Junction Diode11N4148D6 D0-41 Type2A/60V Schottky Diode1SB260D7

Quantity

Ic=600mA, Vce=30V

1A/1000V Junction Rectifier

Description

TO-92 TypeKSP2222AQ1

DO41 Type1N4007D1,D2,D3,D4

Requirement/CommentPart #Reference

TO-92 Type, LM431Vref=2.495V(Typ.)1KA431AZU2

Iover=0.3A, Fairchildsemi0.5A/700V1FSD210

(FSD200)

-CTR 80~160%1H11A817AU3

DO41 Type1A/1000V Ultra Fast Diode1UF4007D5 D0-213 Type10mA/100V Junction Diode11N4148D6 D0-41 Type2A/60V Schottky Diode1SB260D7

Quantity

Ic=600mA, Vce=30V

1A/1000V Junction Rectifier

Description

TO-92 TypeKSP2222AQ1

DO41 Type1N4007D1,D2,D3,D4

Requirement/CommentPart #Reference

CORE : EE1616 BOBBIN : EE1616(H)

W4 W3 W2 W1

2mm 2mm

W4 W3 W2 W1

2mm 2mm

1111

2222

3333

4444

8888

7777

6666

5555

1111

2222

3333

4444

8888

7777

6666

5555

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts

SOLENOID WINDING9 Ts0.40ΦΧ18 →7W4

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts

SOLENOID WINDING50 Ts0.16ΦΧ11 →openW3

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts

CENTER SOLENOID

WINDING

18 Ts0.16ΦΧ14 →3W2

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts

SOLENOID WINDING99 Ts0.16ΦΧ11 →2W1

Wi ndi n g Met hodWinding MethodTurnsTurnsWireWirePin (S Pin (S

→→→→→→→→

F)F)No.No.

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts

SOLENOID WINDING9 Ts0.40ΦΧ18 →7W4

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 3Ts

SOLENOID WINDING50 Ts0.16ΦΧ11 →openW3

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts

CENTER SOLENOID

WINDING

18 Ts0.16ΦΧ14 →3W2

INSULATION : POLYESTER TAPE t=0.025mm / 10mm, 2Ts

SOLENOID WINDING99 Ts0.16ΦΧ11 →2W1

Wi ndi n g Met hodWinding MethodTurnsTurnsWireWirePin (S Pin (S

→→→→→→→→

F)F)No.No.

3,4, 7,8 shor t

100kHz, 1V

50uH1 –2LEAKAGE L

1kHz, 1V1.6mH1 –2INDUCTANCE

REMARKSREMARKSSPECIFICAT IONSPECIFICAT IONTERMINALTERMINALITEMITEM

3,4, 7,8 shor t

100kHz, 1V

50uH1 –2LEAKAGE L

1kHz, 1V1.6mH1 –2INDUCTANCE

REMARKSREMARKSSPECIFICAT IONSPECIFICAT IONTERMINALTERMINALITEMITEM

3,4, 7,8 shor t

100kHz, 1V

50uH1 –2LEAKAGE L

1kHz, 1V1.6mH1 –2INDUCTANCE

REMARKSREMARKSSPECIFICAT IONSPECIFICAT IONTERMINALTERMINALITEMITEM

3,4, 7,8 shor t

100kHz, 1V

50uH1 –2LEAKAGE L

1kHz, 1V1.6mH1 –2INDUCTANCE

REMARKSREMARKSSPECIFICAT IONSPECIFICAT IONTERMINALTERMINALITEMITEM

Page 14

FSD210, FSD200

Typical application circuit

Features

• Non isolation buck converter

• Low component count

• Enhanced system reliability through various protection functions

Key Design Notes

• The output voltage(12V) is regulated with resistors, R1, R2 and R3, zener diode, D3, the transistor, Q1 and the capacitor, C2. While the FSD210 is off diodes, D1 and D2, are on. At this time the output voltage, 12V , can be sensed by the feedback components above. This output is also used with bias voltage for the FSD210.

• R, 680K, is to prevent the OLP(over load protection) at startup.

• R, 8.2K, is a dummy resistor to regulate output voltage in light load.

1. Schematic

2. Demo Circuit Part List

Application Output power Input voltage Output voltage (Max current)

Non Isolation Buck 1.2W

Universal dc input

(100 ~ 375Vac)

12V (100mA)

R 680K

110

4.7uF/400V

8.2K

750

D3(ZD)

1N759A

GND

Q1 KSP2222A

1000uF 16V

47nF/50V

GND

R1 110

FSD21x

142

Vstr

Vcc

Drain

GND

Vfb

GND

C5 47uF 50V

UF4004

VINDC

UF4004

VOUT(12V/100mA)

1mH

TO-92 Type1Q1 DO-35 Type

12VZD/0.5W11N759AZD1

0.5A/700V1FSD210U1

Quantity

1 A/1 000V Ultra F a st Diode

Description

DO 41 TypeUF4007D1,D2,

Requirement/CommentPart #Reference

Ic=200mA, Vcc=40V

1KSP2222A 1

Iover=0.3A

Quantity1Description

DO 41 TypeD1,D2

Requirement/CommentPart #Reference

Page 15

FSD210, FSD200

Layout Considerations (for Flyback Convertor)

Figure 17. Layout Considerations for FSD2x0 us i ng 7DIP

#1 : GND #2 : GND #3 : GND #4 : Vfb #5 : Vcc #6 : N.C. #7 : Drain #8 : Vstr

Copper area for heatsin

Page 16

FSD210, FSD200

Package Dimensions

7-DIP

Page 17

FSD210, FSD200

Package Dimensions

(Continued)

7-LSOP

Page 18

FSD210, FSD200

6/21/04 0.0m 001

 2004 Fairchild Semiconductor Corporation

LIFE SUPPORT POL I CY

FAIRCHILD’S PRODUCTS ARE NOT AUTHOR IZ ED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein :

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expec ted to cause the failur e of the life support device or system, or to affect its safety or effec tiv eness.

www.fairchildsemi.com

DISCLAIMER

FAIRCHILD SEMICON DUCTOR RESERVES THE R I GHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABI LI TY, FUNCTION OR DESIG N. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

Ordering Information

Product Number Package Rating Topr (°C)

FSD210 7DIP 700V, 0.5A −25°C to +85°C

FSD200 7DIP 700V, 0.5A −25°C to +85°C FSD210M 7LSOP 700V, 0.5A −25°C to +85°C FSD200M 7LSOP 700V, 0.5A −25°C to +85°C

Page 19

This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.