Fairchild FSAM50SM60A, Motion SPM 2 Series User Manual

©2006 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

January 2014

FSAM50SM60A
Motion SPM

®

2 Series

Features

• UL Certified No. E209204 (UL1557)

• 600 V - 50 A 3-Phase IGBT Inverter with Integral
Gate Drivers and Protection

• Low-Loss, Short-Circuit Rated IGBTs

• Very Low Thermal Resistance Using Al

2O3

DBC

Substrate

• Separate Open-Emitter Pins from Low Side IGBTs
for Three-Phase Current Sensing

• Single-Grounded Power Supply

• Optimized for 5 kHz Switching Frequency

• Built-in NTC Thermistor for Temperature
Monitoring

• Inverter Power Rating of 4.0 kW / 100~253 VAC

• Adjustable Current Protection Level via Selection
of Sense-IGBT Emitter's External Rs

• Isolation Rating: 2500 V

rms

/ min.

Applications

• Motion Control - Home Appliance / Industrial Motor

Resource

• AN-9043 - Motion SPM® 2 Series User's Guide

General Description

FSAM50SM60A is a Motion SPM® 2 module
providing a fully-featured, high-performance inverter
stage for AC Induction, BLDC, and PMSM motors.
These modules integrate optimized gate drive of
the built-in IGBTs to minimize EMI and losses, while
also providing multiple on-module protection
features including under-voltage lockouts, over­current shutdown, thermal monitoring, and fault
reporting. The built-in, high-speed HVIC requires
only a single supply voltage and translates the
incoming logic-level gate inputs to the high-voltage,
high-current drive signals required to properly drive
the module's internal IGBTs. Separate negative
IGBT terminals are available for each phase to
support the widest variety of control algorithms.

Package Marking and Ordering Information

Device Device Marking Package Packing Type Quantity

FSAM50SM60A FSAM50SM60A S32CA-032 Rail 8

Figure 1. Package Overview

©2006 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Integrated Power Functions

• 600V - 50 A IGBT inverter for three-phase DC / AC power conversion (please refer to Figure 3)

Integrated Drive, Protection and System Control Functions

• For inverter high-side IGBTs: gate drive circuit, high-voltage isolated high-speed level shifting

control circuit Under-Voltage Lock-Out (UVLO) Protection
Note) Available bootstrap circuit example is given in Figures 13 and 14.

• For inverter low-side IGBTs: gate drive circuit, Short-Circuit Protection (SCP)

control supply circuit Under-Voltage Lock-Out (UVLO) Protection

• Temperature Monitoring: system temperature monitoring using built-in thermistor

Note) Available temperature monitoring circuit is given in Figure 14.

• Fault signaling: corresponding to a SC fault (low-side IGBTs) and UV fault (low-side control supply)

• Input interface: active-LOW Interface, works with 3.3 / 5 V logic, Schmitt-trigg er input

Pin Configuration

Figure 2. Top View

Case Temperature(TC)
Detecting Point

(26)N

U

(22)V

B(W)

(1)V

CC(L)

(2)COM

(L)

(3)IN

(UL)

(4)IN

(VL)

(5)IN

(WL)

(7)V

FO

(27)N

V

(28)N

W

(32)P

(20)IN

(WH)

(23)V

S(W)

(29)U

(30)V

(31)W

(8)C

FOD

(9)C

SC

(25)R

TH

(24)V

TH

(21)V

CC(WH)

(18)V

B(V)

(19)V

S(V)

(15)IN

V(H)

(17)V

CC(VH)

(16)COM

(H)

(13)V

B(U)

(14)V

S(U)

(11)IN

(UH)

(12)V

CC(UH)

(10)R

SC

(6)COM

(L)

DBC Substrate

Case Temperature(T

C

)

Detecting Point

(26)N

U

(22)V

B(W)

(1)V

CC(L)

(2)COM

(L)

(3)IN

(UL)

(4)IN

(VL)

(5)IN

(WL)

(7)V

FO

(27)N

V

(28)N

W

(32)P

(20)IN

(WH)

(23)V

S(W)

(29)U

(30)V

(31)W

(8)C

FOD

(9)C

SC

(25)R

TH

(24)V

TH

(21)V

CC(WH)

(18)V

B(V)

(19)V

S(V)

(15)IN

V(H)

(17)V

CC(VH)

(16)COM

(H)

(13)V

B(U)

(14)V

S(U)

(11)IN

(UH)

(12)V

CC(UH)

(10)R

SC

(6)COM

(L)

DBC Substrate

©2006 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Pin Descriptions

Pin Number Pin Name Pin Description

1V

CC(L)

Low-Side Common Bias Voltage for IC and IGBTs Driving

2COM

(L)

Low-Side Common Supply Ground

3IN

(UL)

Signal Input Terminal for Low-Side U-Phase

4IN

(VL)

Signal Input Terminal for Low-Side V-Phase

5IN

(WL)

Signal Input Terminal for Low-Side W-Phase

6COM

(L)

Low-Side Common Supply Ground

7V

FO

Fault Output

8C

FOD

Capacitor for Fault Output Duration Selection

9C

SC

Capacitor (Low-Pass Filter) for Short-Circuit Current Detection Input

10 R

SC

Resistor for Short-Circuit Current Detection

11 IN

(UH)

Signal Input for High-Side U-Phase

12 V

CC(UH)

High-Side Bias Voltage for U-Phase IC

13 V

B(U)

High-Side Bias Voltage for U-Phase IGBT Driving

14 V

S(U)

High-SideBias Voltage Ground for U-Phase IGBT Driving

15 IN

(VH)

Signal Input for High-Side V-Phase

16 COM

(H)

High-Side Common Supply Ground

17 V

CC(VH)

High-Side Bias Voltage for V-Phase IC

18 V

B(V)

High-Side Bias Voltage for V-Phase IGBT Driving

19 V

S(V)

High-Side Bias Voltage Ground for V-Phase IGBT Driving

20 IN

(WH)

Signal Input for High-side W-Phase

21 V

CC(WH)

High-Side Bias Voltage for W-Phase IC

22 V

B(W)

High-Side Bias Voltage for W-Phase IGBT Driving

23 V

S(W)

High-Side Bias Voltage Ground for W-Phase IGBT Driving

24 V

TH

Thermistor Bias Voltage

25 R

TH

Series Resistor for the Use of Thermistor (Temperature Detection)

26 N

U

Negative DC-Link Input Terminal for U-Phase

27 N

V

Negative DC-Link Input Terminal for V-Phase

28 N

W

Negative DC-Link Input Terminal for W-Phase
29 U Output for U-Phase
30 V Output for V-Phase
31 W Output for W-Phase
32 P Positive DC-Link Input

©2006 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Internal Equivalent Circuit and Input/Output Pins

Figure 3. Internal Block Diagram

1st Notes:

1. Inverter low-side is composed of three sense-IG BTs includ ing free whe eling d iodes for each IGBT a nd one co ntrol IC w hich has ga te drivi ng, cur rent -sensing and
protection functions.

2. Inverter power side is composed of four inverter DC-link input pins and three inverter output pins.

3. Inverter high-side is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT.

COM(L)
VCC

IN(UL)

IN(VL)

IN(WL)

VFO

C(FOD)

C(SC)

OUT(UL)

OUT(VL)

OUT(WL)

NU (26)

N

V

(27)

N

W

(28)

U (29)

V (30)

W (31)

P (32)

(23) V

S(W)

(22) V

B(W)

(19) V

S(V)

(18) V

B(V)

(9) C

SC

(8) C

FOD

(7) V

FO

(5) IN

(WL)

(4) IN

(VL)

(3) IN

(UL)

(2) COM

(L)

(1) V

CC(L)

(10) R

SC

RTH (25)

V

TH

(24)

(6) COM

(L)

VCC

VB

OUT

COM

VS

IN

VB

VS

OUT

IN

COM

VCC

VCC

VB

OUT

COM

VS

IN

(21) V

CC(WH)

(20) IN

(WH)

(17) V

CC(VH)

(15) IN

(VH)

(16) COM

(H)

(14) V

S(U)

(13) V

B(U)

(12) V

CC(UH)

(11) IN

(UH)

THERMISTOR

©2006 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Absolute Maximum Ratings (T

J

= 25°C, unless otherwise specified.)

Inverter Part

2nd Notes:

1. It would be recommended that the average junction temperature should be limited to TJ  125C (at TC  100C) in order to guarantee safe operation.

Control Part

Total System

Thermal Resistance

2nd Notes:

2. For the measurement point of case temperature(TC), please refer to Figure 2.

3. The thickness of thermal grease should not be more than 100 m.

Item Symbol Condition Rating Unit

Supply Voltage V

DC

Applied to DC-Link 450 V

Supply Voltage (Surge) V

PN(Surge)

Applied between P and N 500 V

Collector - Emitter Voltage V

CES

600 V

Each IGBT Collector Current ± I

C

TC = 25°C 50 A

Each IGBT Collector Current ± I

C

TC = 100°C 25 A

Each IGBT Collector Current (Peak) ± I

CP

TC = 25°C , Under 1ms Pulse Width 100 A

Collector Dissipation P

C

TC = 25°C per Chip 100 W

Operating Junction Temperature T

J

(2nd Note 1) -20 ~ 125 °C

Item Symbol Condition Rating Unit

Control Supply Voltage V

CC

Applied between V

CC(UH)

, V

CC(VH)

, V

CC(WH)

-

COM

(H)

, V

CC(L)

- COM

(L)

20 V

High-Side Control Bias Voltage V

BS

Applied between V

B(U)

- V

S(U)

, V

B(V)

- V

S(V)

, V

B(W)

-

V

S(W)

20 V

Input Signal Voltage V

IN

Applied between IN

(UH)

, IN

(VH)

, IN

(WH)

- COM

(H)

IN

(UL)

, IN

(VL)

, IN

(WL)

- COM

(L)

-0.3 ~ VCC+0.3 V

Fault Output Supply Voltage V

FO

Applied between VFO - COM

(L)

-0.3 ~ VCC+0.3 V

Fault Output Current I

FO

Sink Current at VFO Pin 5 mA

Current-Sensing Input Voltage V

SC

Applied between CSC - COM

(L)

-0.3 ~ VCC+0.3 V

Item Symbol Condition Rating Unit

Self-Protection Supply Voltage Limit
(Short-Circuit Protection Capability)

V

PN(PROT)

Applied to DC-Link,
V

CC

= VBS = 13.5 ~ 16.5 V

T

J

= 125°C, Non-Repetitive, < 5 s

400 V

Module Case Operation Temperature T

C

See Figure 2 -20 ~ 100 °C

Storage Temperature T

STG

-20 ~ 125 °C

Isolation Voltage V

ISO

60Hz, Sinusoidal, AC 1 Minute, Connect
Pins to Heat Sink Plate

2500 V

rms

Item Symbol Condition Min. Typ. Max. Unit

Junction to Case Thermal
Resistance

R

th(j-c)Q

Inverter IGBT Part (per 1/6 module) - - 1.00 °C/W

R

th(j-c)F

Inverter FWDi Part (per 1/6 module) - - 1.50 °C/W

Contact Thermal
Resistance

R

th(c-f)

DBC Substrate (per 1 Module)
Thermal Grease Applied (2nd Note 3)

- - 0.06 °C/W

©2006 Fairchild Semiconductor Corporation 6 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Electrical Characteristics

Inverter Part (T

J

= 25°C, unless otherwise specified.)

2nd Notes:

4. tON and t

OFF

include the propagation delay time of the internal drive IC. t

C(ON)

and t

C(OFF)

are the switching time of IGBT itself under the given gate driving condition

internally. For the detailed information, please see Figure 4.

Figure 4. Switching Time Definition

Item Symbol Condition Min. Typ. Max. Unit

Collector - emitter
Saturation Voltage

V

CE(SAT)VCC

= VBS = 15 V

V

IN

= 0 V

I

C

= 50 A, TJ = 25°C - - 2.4 V

FWDi Forward Voltage V

FMVIN

= 5 V IC = 50 A, TJ = 25°C - - 2.1 V

Switching Times t

ON

VPN = 300 V, VCC = VBS = 15 V
I

C

= 50 A, TJ = 25°C

V

IN

= 5 V  0 V, Inductive Load

(High- And Low-Side)
(2nd Note 4)

-0.69- s

t

C(ON)

-0.32- s

t

OFF

-1.32- s

t

C(OFF)

-0.46- s

t

rr

-0.10- s

Collector-Emitter
Leakage Current

I

CESVCE

= V

CES

, TJ = 25°C - - 250 A

t

rr

I

C

V

CE

V

IN

t

ON

t

C(ON)

V

IN(ON)

10% I

C

90% I

C

10% V

CE

100% I

C

(a) Turn-on

t

rr

I

C

V

CE

V

IN

t

ON

t

C(ON)

V

IN(ON)

10% I

C

90% I

C

10% V

CE

100% I

C

(a) Turn-on (b) Turn-off

I

C

V

CE

V

IN

t

OFF

t

C(OFF)

10% VCE10% I

C

V

IN(OFF)

(b) Turn-off

I

C

V

CE

V

IN

t

OFF

t

C(OFF)

10% VCE10% I

C

V

IN(OFF)

©2006 Fairchild Semiconductor Corporation 7 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Electrical Characteristics (T

J

= 25°C, unless otherwise specified.)

Control Part

2nd Notes:

5. Short-circuit protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be selected
around 40  in order to make the SC trip-level of about 75A at the shunt resistors (RSU, RSV, RSW) of 0. For the detailed information about the relationship
between the external sensing resi stor (RSC) and the shunt resistors (RSU, RSV, RSW), please see Figure 6.

6. The fault-out pulse width t

FOD

depends on the capacitance value of C

FOD

according to the following approximate equation: C

FOD

= 18.3 x 10-6 x t

FOD

[F]

7. TTH is the temperature of thermistor itself. To know case temperature (TC), please make the experiment considering your application.

Figure 5. R-T Curve of The Built-in Thermistor

Item Symbol Condition Min. Typ. Max. Unit

Quiescent VCC Supply Cur­rent

I

QCCLVCC

= 15 V

IN

(UL, VL, WL)

= 5V

V

CC(L)

- COM

(L)

--26mA

I

QCCHVCC

= 15 V

IN

(UH, VH, WH)

= 5V

V

CC(UH)

, V

CC(VH)

, V

CC(WH)

-

COM

(H)

- - 130 A

Quiescent V

BS

Supply Cur-

rent

I

QBSVBS

= 15 V

IN

(UH, VH, WH)

= 5V

V

B(U)

- V

S(U)

, V

B(V)

-V

S(V)

,

V

B(W)

- V

S(W)

- - 420 A

Fault Output Voltage V

FOHVSC

= 0 V, VFO Circuit: 4.7 k to 5 V Pull-up 4.5 - - V

V

FOLVSC

= 1 V, VFO Circuit: 4.7 k to 5 V Pull-up - - 1.1 V

Short-Circuit Trip Level V

SC(ref)VCC

= 15 V (2nd Note 5) 0.45 0.51 0.56 V

Sensing Voltage
of IGBT Current

V

SENRSC

= 40 , RSU = RSV = RSW = 0 and IC = 75 A

(See a Figure 6)

0.45 0.51 0.56 V

Supply Circuit Under­Voltage Protection

UV

CCD

Detection Level 11.5 12.0 12.5 V

UV

CCR

Reset Level 12.0 12.5 13.0 V

UV

BSD

Detection Level 7.3 9.0 10.8 V

UV

BSR

Reset Level 8.6 10.3 12.0 V

Fault Output Pulse Width t

FODCFOD

= 33 nF (2nd Note 6) 1.4 1.8 2.0 ms

ON Threshold Voltage V

IN(ON)

High-Side Applied between IN

(UH)

,

IN

(VH)

, IN

(WH)

- COM

(H)

--0.8V

OFF Threshold Voltage V

IN(OFF)

3.0 - - V

ON Threshold Voltage V

IN(ON)

Low-Side Applied between IN

(UL)

,

IN

(VL)

, IN

(WL)

- COM

(L)

--0.8V

OFF Threshold Voltage V

IN(OFF)

3.0 - - V

Resistance of Thermistor R

TH

@ TTH = 25°C (2nd Note 7, Figure 5) - 50 - k
@ T

TH

= 100°C (2nd Note 7, Figure 5) - 3.0 - k

20 30 40 50 60 70 80 90 100 110 120

0

10k

20k

30k

40k

50k

60k

70k

R-T Curve

Resistance[]

Temperature TTH[]℃

©2006 Fairchild Semiconductor Corporation 8 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Figure 6. RSC Variation by Change of Shunt Resistors ( RSU, RSV, RSW) for Short-Circuit Protection

(1) @ Current Trip Level ≒ 50 A
(2) @ Current Trip Level ≒ 75 A

Recommended Operating Conditions

2nd Notes:

8. Motion SPM® 2 product might not make response if the PW

IN(OFF)

is less than the recommended minimum value.

Item Symbol Condition Min. Typ. Max. Unit

Supply Voltage V

PN

Applied between P - NU, NV, N

W

- 300 400 V

Control Supply Voltage V

CC

Applied between V

CC(UH)

, V

CC(VH)

, V

CC(WH)

-

COM

(H)

, V

CC(L)

- COM

(L)

13.5 15.0 16.5 V

High-side Bias Voltage V

BS

Applied between V

B(U)

- V

S(U)

, V

B(V)

- V

S(V)

,

V

B(W)

- V

S(W)

13.0 15.0 18.5 V

Blanking Time for Preventing
Arm-short

t

dead

For Each Input Signal 3.5 - - s

PWM Input Signal f

PWMTC

 100°C, TJ 125°C - 5 - kHz

Minimum Input Pulse Width PW

IN(OFF)

200 VPN  400 V, 13.5  VCC  16.5 V,

13.0  V

BS

 18.5 V, IC  100 A,

-20  T

J

 125°C

V

IN

= 5 V  0 V, Inductive Load (2nd Note 8)

3--s

Input ON Threshold Voltage V

IN(ON)

Applied between IN

(UH)

, IN

(VH)

, IN

(WH)

-

COM

(H)

, IN

(UL)

, IN

(VL)

, IN

(WL)

- COM

(L)

0 ~ 0.65 V

Input OFF Threshold Voltage V

IN(OFF)

Applied between IN

(UH)

, IN

(VH)

, IN

(WH)

-

COM

(H)

, IN

(UL)

, IN

(VL)

, IN

(WL)

- COM

(L)

4 ~ 5.5 V

0.000 0.005 0.010 0.015 0.020 0.025 0.030

0

20

40

60

80

(2)

(1)

Rsu,Rsv,Rsw []

R

sc

[]

©2006 Fairchild Semiconductor Corporation 9 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Mechanical Characteristics and Ratings

Figure 7. Flatness Measurement Position of The DBC Substrate

2nd Notes:

9. Do not make over torque or mounting screws. Much mounting torque may cause DBC substrate cracks and bolts and Al heat-sink destruction.

10.Avoid one side tightening stress. Figure 8 shows the recommended torque order for mounting screws. Uneven mounting can cause the Motion SPM® 2 package
DBC substrate to be damaged.

Figure 8. Mounting Screws Torque Order (1  2)

Item Condition Min. Typ. Max. Units

Mounting Torque Mounting Screw: M4

(2nd Note 9 and 10)

Recommended 10 kg•cm 8 10 12 kg•cm

Recommended 0.98 N•m 0.78 0.98 1.17 N•m
DBC Flatness See Figure 7 0 - +120 m
Weight -32-g

(+)

(+)

(+)

(+)

(+)

(+)

(+)

(+)

(+)

121

2

©2006 Fairchild Semiconductor Corporation 10 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Time Charts of Protective Function

P1 : Normal operation: IGBT ON and conducting current .
P2 : Under-voltage detection.
P3 : IGBT gate interrupt.
P4 : Fault signal generation.
P5 : Under-voltage reset.
P6 : Normal operation: IGBT ON and conducting current.

Figure 9. Under-Voltage Protection (Low-Side)

P1 : Normal operation: IGBT ON and conducting current.
P2 : Under-voltage detection.
P3 : IGBT gate interrupt.
P4 : No fault signal.
P5 : Under-voltage reset.
P6 : Normal operation: IGBT ON and conducting current.

Figure 10. Under-Voltage Protection (High-Side)

Internal IGBT

Gate-Emitter Voltage

Input Signal

Output Current

Fault Output Signal

Control Supply Voltage

P1

P2

P3

P4

P6

P5

UV

detect

UV

reset

Internal IGBT

Gate-Emitter Voltage

Input Signal

Output Current

Fault Output Signal

Control Supply Voltage

V

BS

P1

P2

P3

P4

P6

P5

UV

detect

UV

reset

©2006 Fairchild Semiconductor Corporation 11 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

P1 : Normal operation: IGBT ON and conducting current.
P2 : Short-circuit current detection.
P3 : IGBT gate interrupt / fault signal generation.
P4 : IGBT is slowly turned off.
P5 : IGBT OFF signal.
P6 : IGBT ON signal: but IGBT cannot be turned on during the fault-output activation.
P7 : IGBT OFF state.
P8 : Fault-output reset and normal operation start.

Figure 11. Short-Circuit Protection (Low-Side Operation Only)

Figure 12. Recommended MCU I/O Interface Circuit

3rd Notes:

1. It would be recommended that by-pass capacitors for the gating input signals, IN

(UL)

, IN

(VL)

, IN

(WL)

, IN

(UH)

, IN

(VH)

and IN

(WH)

should be placed on the Motion

SPM® 2 product pins and on the both sides of MCU and Motion SPM 2 Product for the fault output signal, VFO, as close as possible.

2. The logic input works with standard CMOS or LSTTL outputs.

3. RPLCPL/RPHCPH/RPFC

PF

coupling at each Motion SPM 2 product input is recommended in order to preve nt in put/output signals’ oscillation and it should be as

close as possible to each of Motion SPM 2 Product pins.

Internal IGBT

Gate-Emitter Voltage

Input Signal

Output Current

Sensing Voltage

Fault Output Signal

P1

P2

P3

P4

P6

P5

P7

P8

SC Reference

Voltage (0.5V)

RC Filter Delay

SC Detection

MCU

COM

5 V

1.2 nF0.47 nF1 nF

4.7 k

,,

IN

(UL)IN(VL)

IN

(WL)

,,

IN

(UH)IN(VH)

IN

(WH)

V

FO

100 

1 nF

SPM

2 k

R

PF

=R

PL

=RPH=

C

PF

=C

PL

=C

PH

=

100 

100 

4.7 k

©2006 Fairchild Semiconductor Corporation 12 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Figure 13. Recommended Bootstrap Operation Circuit and Parameters

3rd Notes:

4. It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics.

5. The bootstrap resistor(RBS) should be three times greater than R

E(H)

. The recommended value of R

E(H)

is 5.6, but it can be increas ed u p to 20Ω for a slower dv/

dt of high-side.

6. The ceramic capacitor pla ced between V

CC

- COM should be over 1 F and mounted as close to the pins of the Motion SPM® 2 product as possible.

15 V

47

µF

0.1

µF

470

µF1 µF

One-Leg Diagram of
Motion SPM

®

2 Product

Vcc

IN

COM

VB

HO

VS

Vcc

IN

COM

OUT

Inverter

Output

P

N

These values depend on PWM control algorithm

D

BS

R

E(H)

R

BS

©2006 Fairchild Semiconductor Corporation 13 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Figure 14. Application Circuit

4th Notes:

1. RPLCPL/RPHCPH /RPFCPF coupling at each Motion SPM® 2 product input is recommended in order to prevent input signals’ oscillation and it should be as close as
possible to each Motion SPM 2 product input pin.

2. By virtue of integrating an ap plicatio n specific type HVIC inside the Motion SP M 2 product, direct co upling to MC U termina ls without any o ptocoupler or transformer
isolation is possible.

3. VFO output is open-collector type. This signal line should be pulled up to the positive side of the 5 V power supply with approximately 4.7 k resistance. Please
refer to Figure 12.

4. C

SP15

of around seven times larger than bootstrap capacitor CBS is recommended.

5. VFO output pulse width should be determined by connectin g an external capacitor( C

FOD

) between C

FOD

(pin 8) and COM

(L)

(pin 2). (Example : if C

FOD

= 33 nF, then

tFO = 1.8 ms (typ.)) Please refer to the 2nd note 6 for calculation method.

6. Each input signal line should be pulled up to the 5 V power supply with approximately 4.7 k (at high side input) or 2 kat low side input) resistance (other RC
coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system’s printed circuit board).
Approximately a 0.22 ~ 2 nF by-pass capacitor should be used across each power supply connection terminals.

7. To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible.

8. In the short-circuit protection circuit, please select the RFCSC time constant in the range 3 ~ 4 s.

9. Each capacitor should be mounted as close to the pins of the Motion SPM 2 product as possible.

10. To prevent surge destruction, the wiring between the smoothing capacitor and the P & N pins should be as short as possible. The use of a high frequency non­inductive capacitor of around 0.1 ~ 0.22 F between the P&N pins is recommended.

11. Relays are used at almost every systems of electrical equipments of home appliances . In these cases, there sh ould be su fficient dista nce betwee n the M CU and
the relays. It is recommended that the distance be 5 cm at least.

COM(L)
VCC

IN(UL)

IN(VL)

IN(WL)

VFO

C(FOD)

C(SC)

OUT(UL)

OUT(VL)

OUT(WL)

NU(26)

N

V

(27)

N

W

(28)

U (29)

V (30)

W (31)

P (32)

(23) V

S(W)

(22) V

B(W)

(19) V

S(V)

(18) V

B(V)

(9) C

SC

(8) C

FOD

(7) V

FO

(5) IN

(WL)

(4) IN

(VL)

(3) IN

(UL)

(2) COM

(L)

(1) V

CC(L)

(10) R

SC

VTH(24)
R

TH

(25)

(6) COM

(L)

VCC

VB

OUT

COM

VS

IN

VB

VS

OUT

IN

COM

VCC

VCC

VB

OUT

COM

VS

IN

(21) V

CC(WH)

(20) IN

(WH)

(17) V

CC(VH)

(15) IN

(VH)

(16) COM

(H)

(14) V

S(U)

(13) V

B(U)

(12) V

CC(UH)

(11) IN

(UH)

Fault

15 V

C

BS

C

BSC

RBSD

BS

CBSC

BSC

RBSD

BS

C

BS

C

BSC

R

BS

D

BS

C

SP15

C

SPC15

C

FOD

5 V

R

PF

C

PL

C

BPF

RPLRPLR

PL

CPLC

PL

5 V

C

PH

R

PH

C

PH

R

PH

C

PH

R

PH

R

S

R

S

R

S

R

S

R

S

R

S

R

S

M

Vdc

C

DCS

5 V

R

TH

C

SP05

C

SPC05

THERMISTOR

Temp. Monitoring

Gating UH

Gating VH

Gating WH

Gating WH

Gating VH
Gating UH

C

PF

M
C
U

R

FU

R

FV

R

FW

R

SU

R

SV

R

SW

C

FU

C

FV

C

FW

W-Phase Current

V-Phase Current
U-Phase Current

R

F

C

SC

R

SC

R

CSC

R

E(WH)

R

E(VH)

R

E(UH)

©2006 Fairchild Semiconductor Corporation 14 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series

Detailed Package Outline Drawings

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any
manner without notice. Please note the revision and/or data on the drawing and contact a FairchildSemiconductor
representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s
worldwide therm and conditions, specifically the the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/dwg/MO/MOD32BA.pdf

©2006 Fairchild Semiconductor Corporation 15 www.fairchildsemi.com

FSAM50SM60A Rev. C4

FSAM50SM60A Motion SPM® 2 Series