D r a i n C u r r e n t - P u l s e d (Note 1)0.8A
Single Pulsed Avalanche Energy (Note 2)33mJ
Avalanche Current (Note 1)0.2A
Repetitive Avalanche Energy (Note 1)0.2mJ
Power Dissipation
Operating and Storage Temperature Range-55 to +150
Maximum Lead Temperature for Soldering Purpose,
1/8” from Case for 5 Seconds
Description
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild’s proprietary, planar
stripe, DMOS technology.
This advanced technology has been especially tailored to
minimize on-state resistance, provide superior switching
performance, and withstand high energy pulse in the avalanche
and commutation mode. These devices are well suited for high
efficient switched mode power supplies and active power factor
correction.
D
G
S
= 25oC)0.2
C
= 100oC)0.12
C
o
C0.02W/
300
o
o
A
o
C
C
C
Thermal Characteristics
SymbolParameter
R
θJA
* When mounted on the minimum pad size recommended (PCB Mount)
Figure 7. Breakdown Voltage Variation Figure 8. On-Resistance Variation
vs. Temperature vs. Temperature
1.2
1.1
3.0
2.5
2.0
FQT1N60C N-Channel MOSFET
1.0
, (Normalized)
DSS
BV
0.9
Drain-Source Breakdown Voltage
0.8
-100- 5005010015 0200
Notes :※
1. VGS = 0 V
2. I
= 250 µ A
D
TJ, Juncti on Temperatur e [oC]
1.5
, (Normalized)
1.0
DS(ON)
R
Drain-Source On-Resistance
0.5
0.0
-100-50050100150200
TJ, Junct ion Temperature [oC]
Notes :※
1. VGS = 10 V
2. I
= 0.1 A
D
Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current
vs. Case Temperature
, Drain Current [A]
D
I
Operation i n This Area
is Li mited by R
0
10
DS(on)
100 µs
1 ms
1 s
10 ms
100 ms
-1
10
DC
-2
10
-3
10
0
10
1. TC = 25 oC
2. T
3. Singl e Pulse
1
10
Note s :※
= 150 oC
J
2
10
3
10
0.20
0.18
0.16
0.14
0.12
0.10
0.08
, Drain Current [A]
0.06
D
I
0.04
0.02
0.00
255075100125150
VDS, Drai n-Source Vol tage [ V]
TC, Case Temperature [°C]
Figure 11. Transient Thermal Response Curve
No tes :※
1. Z
(t) = 6 0 /W M ax.℃
θ JC
2. D uty Fa cto r, D= t1/t
3. TJM - TC = PDM * Z
P
DM
t
1
t
2
-2
-1
10
0
10
1
10
4
FQT1N60C Rev. A
2
10
D=0.5
0.2
1
10
0.1
0.05
0.02
0
10
0.01
(t), Thermal Response
θ JC
Z
-1
10
-5
10
10
-4
single pulse
-3
10
10
t1, Square Wave Pulse Duration [sec]
2
(t)
θ JC
2
10
3
10
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Gate Charge Test Circuit & Waveform
Resistive Switching Test Circuit & Waveforms
FQT1N60C N-Channel MOSFET
FQT1N60C Rev. A
Unclamped Inductive Switching Test Circuit & Waveforms
5
www.fairchildsemi.com
Peak Diode Recovery dv/dt Test Circuit & Waveforms
g
g
+
+
V
V
DS
DS
_
_
L
LL
Sam e Type
Sam e Type
as DU T
as DU T
• dv/dt controlled by R
• dv/dt controlled by R
•ISDcontrolled by pulse period
•ISDcontrolled by pulse period
G
G
V
V
GS
GS
R
R
G
G
DUT
DUT
I
I
SD
SD
Driver
Driver
V
V
DD
DD
FQT1N60C N-Channel MOSFET
V
V
GS
GS
( D riv er )
( D riv er )
I
I
SD
SD
( DUT )
( DUT )
V
V
DS
DS
( DUT )
( DUT )
G ate P ulse W idth
G ate P ulse W idth
G ate P ulse W idth
--------------------------
--------------------------
--------------------------
D =
D =
D =
Gate Pulse Period
Gate Pulse Period
Gate Pulse Period
IFM, B ody Diode Forw ard C urrent
IFM, B ody Diode Forw ard C urrent
I
I
RM
RM
Body D iode R everse C urrent
Body D iode R everse C urrent
Body D iode R ecovery dv/dt
Body D iode R ecovery dv/dt
V
V
SD
SD
Body Diode
Body Diode
e D rop
Forward Volta
Forward Volta
e D rop
di/dt
di/dt
10V
10V
V
V
DD
DD
FQT1N60C Rev. A
6
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Mechanical Dimensions
1
FQT1N60C N-Channel MOSFET
SOT-223
3.00 ±0.10
2.30 TYP
(0.95)(0.95)
4.60 ±0.25
0.70 ±0.10
MAX1.80
±0.20
1.75
±0.20
3.50
(0.60)(0.60)
0.25
+0.10
–0.05
0.08MAX
0.65 ±0.20
+0.04
0.06
–0.02
0°~10°
7.00 ±0.30
6.50 ±0.20
.60 ±0.20
(0.46)
(0.89)
FQT1N60C Rev. A
7
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TRADEMARKS
®
The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or (b)
support or sustain life, and (c) whose failure to perform when
properly used in accordance with instructions for use provided
2. A critical component in any component of a life support,
device, or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
in the labeling, can be reasonably expected to result in a
significant injury to the user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet IdentificationProduct StatusDefinition
Advance InformationFormative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
This datasheet contains preliminary data; supplementary data will be pub-
PreliminaryFirst Production
lished at a later date. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve design.
No Identification NeededFull Production
This datasheet contains final specifications. Fairchild Semiconductor reserves
the right to make changes at any time without notice to improve design.
This datasheet contains specifications on a product that has been discontin-
ObsoleteNot In Production
ued by Fairchild Semiconductor. The datasheet is printed for reference information only.
Rev. I31
FQT1N60C Rev. A
8
www.fairchildsemi.com
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