Programmable logic control
Isolated data acquisition system
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■
Voltage level translator
Isolating MOSFET/IGBT gate drivers
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2
C
Description
The FODM611 is a 5V high-speed logic gate output
(open collector) optocoupler, which supports isolated
communications allowing digital signals to communicate
between systems without conducting ground loops or
hazardous voltages. It utilizes Fairchild’s proprietary
coplanar packaging technology, Optoplanar
optimized IC design to achieve high noise immunity,
characterized by high common mode transient immunity
specifications.
This optocoupler consists of an AlGaAS LED at the
input, optically coupled to a high speed integrated photodetector logic gate. The output of the detector IC is an
open collector schottky-clamped transistor. The coupled
parameters are guaranteed over the wide temperature
range of -40°C to +85°C. A maximum input signal of
5mA will provide a minimum output sink current of 13mA
(fan out of 8).
Safety and Insulation Ratings for Mini-Flat Package (SO5 Pin)
As per IEC60747-5-2 (Pending Certification). This optocoupler is suitable for “safe electrical insulation” only within the
safety limit data. Compliance with the safety ratings shall be ensured by means of protective circuits.
SymbolParameterMin.Typ.Max.Unit
Installation Classifications per DIN VDE 0110/1.89 Table 1
For rated main voltage < 150VrmsI-IV
For rated main voltage < 300VrmsI-III
Climatic Classification40/85/21
Pollution Degree (DIN VDE 0110/1.89)2
CTIComparative Tracking Index175
V
V
T
V
PR
V
PR
IORM
IOTM
Case
R
IO
Input to Output Test Voltage, Method b,
VIORM x 1.875 = V
t
= 1 sec, Partial Discharge < 5 pC
m
, 100% Production Test with
PR
Input to Output Test Voltage, Method a,
VIORM x 1.5 = V
t
= 60 sec, Partial Discharge < 5 pC
m
, Type and Sample Test with
PR
Max Working Insulation Voltage565V
Highest Allowable Over Voltage4000V
External Creepage5.0mm
External Clearance5.0mm
Insulation thickness0.5mm
Safety Limit Values, Maximum Values allowed in the event
of a failure, Case Temperature
Insulation Resistance at T
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In
addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
SymbolParameterValueUnits
T
T
T
V
PD
PD
STG
OPR
T
J
SOL
I
F
V
R
CC
V
O
I
O
I
O
Storage Temperature-40 to +125ºC
Operating Temperature-40 to +85ºC
Junction Temperature-40 to +125ºC
Lead Solder Temperature
260 for 10secºC
(Refer to Reflow Temperature Profile)
Forward Current50mA
Reverse Voltage5.0V
Supply Voltage0 to 7.0V
Output Voltage-0.5 to V
+0.5V
CC
Average Output Current50mA
Input Power Dissipation
Output Power Dissipation
(1)(2)
(1)(2)
100mW
85mW
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Logic HIGH Output CurrentIF = 250µA, VO = 5.0V, Fig. 42.130.0µA
OH
Logic LOW Output Supply CurrentIF = 10mA, V
Logic HIGH Output Supply CurrentIF = 0mA, V
Switching Characteristics
(T
= -40ºC to +85ºC, 4.5V ≤ V
A
Typical value is measured at T
5.5V, I
CC
= 25ºC and V
A
(Apply over all recommended conditions)
F
= rated I
F
I
(sinking) = 13mA, Fig. 3
OL
,
FHL
= 5.0V, Fig. 5, 77.510.0mA
CC
= 5.0V, Fig. 6, 76.09.0mA
CC
= 7.5mA), unless otherwise specified.
= 5.0V
CC
0.40.6V
SymbolParameterTest ConditionsMin.Typ.Max.Units
Date RateRL = 350Ω10Mbps
t
PHL
Propagation Delay Time to Logic
Low Output
t
PLH
Propagation Delay Time to Logic
High Output
PWDPulse Width Distortion,
| t
– t
PLH
|
t
PSK
PHL
Propagation Delay SkewRL = 350Ω, CL = 15pF
RL = 350Ω, CL = 15pF,
Fig. 8 and 11
RL = 350Ω, CL = 15pF,
Fig. 8 and 11
= 350Ω, CL = 15pF,
R
L
Fig. 9
(6)
43100ns
50100ns
735ns
40ns
t
R
Output Rise Time, (10% to 90%) RL = 350Ω, CL = 15pF,
20ns
Fig. 10 and 11
t
F
Output Fall Time, (90% to 10%)RL = 350Ω, CL = 15pF,
10ns
Fig. 10 and 11
|Common Mode Transient
|CM
H
Immunity at Output High
|Common Mode Transient
|CM
L
Immunity at Output Low
VI = 5.0V, VO > 0.8 x VCC,
V
= 1000V
CM
VI = 0V, VO < 0.8V,
V
= 1000V
CM
(7)
, Fig. 12
(7)
, Fig. 12
2040kV/µs
2040kV/µs
Notes
6. t
is equal to the magnitude of the worst case difference in t
PSK
PHL
and/or t
that will be seen between any two units
PLH
from the same manufacturing date code that are operated at same case temperature (±5°C), at same operating
conditions, with equal loads (R
= 350Ω and C
L
= 15pF), and with an input rise time less than 5ns.
L
7. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient immunity
at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal, Vcm, to
assure that the output will remain low.