FOD8321 — 2.5A Output Current, Gate Drive Optocoupler in Optoplanar
May 2012
FOD8321
2.5A Output Current, Gate Drive Optocoupler in
®
Optoplanar
Wide Body SOP 5-Pin
Features
Fairchild’s Optoplanar
■
provides reliable and high voltage insulation with
greater than 8mm creepage and clearance distance,
and 0.5mm internal insulation distance while still
offering a compact footprint
2.5A output current driving capability for medium
■
power IGBT/MOSFET
– Use of P-Channel MOSFETs at output stage
enables output voltage swing close to the supply
rail
■
20kV/µs Minimum Common Mode Rejection
Wide Supply Voltage range from 15V to 30V
■
■
Fast Switching Speed over full operating temperature
range
Extended industrial temperate range, -40 to 100°C
temperature range
■
Safety and regulatory approvals
– UL1577, 5,000V
– DIN EN/IEC60747-5-5, 1,414V peak working
insulation voltage
®
packaging technology
for 1 min.
RMS
Applications
■
AC and brushless DC motor drives
Industrial inverter
■
■
Uninterruptible power supply
Induction heating
■
■
Isolated IGBT/Power MOSFET gate drive
Description
The FOD8321 is a 2.5A Output Current Gate Drive
Optocoupler, capable of driving medium power IGBT/
MOSFETs. It is ideally suited for fast switching driving of
power IGBT and MOSFETs used in motor control
inverter applications, and high performance power
systems.
It utilizes Fairchild’s coplanar packaging technology,
Optoplanar
high insulation voltage and high noise immunity.
It consists of a aluminum gallium arsenide (AlGaAs) light
emitting diode optically coupled to an integrated circuit
with a high-speed driver for push-pull MOSFET output
stage. The device is housed in a wide body 5-pin small
outline plastic package.
As per DIN EN/IEC60747-5-5. This optocoupler is suitable for “safe electrical insulation” only within the safety limit
data. Compliance with the safety ratings shall be ensured by means of protective circuits.
SymbolParameter Min.Typ.Max.Unit
Pollution Degree (DIN VDE 0110/1.89)2
CTIComparative Tracking Index175
V
PR
V
IORM
V
IOTM
External Creepage8.0 mm
External Clearance8.0 mm
Insulation Thickness0.5 mm
T
S
I
S,INPUT
P
S,OUTPUT
R
IO
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150VrmsI–IV
For Rated Mains Voltage < 300VrmsI–IV
For Rated Mains Voltage < 450VrmsI–IIII
For Rated Mains Voltage < 600VrmsI–III
Climatic Classification40/100/21
Input to Output Test Voltage, Method b,
V
x 1.875 = V
IORM
t
= 1 sec., Partial Discharge < 5pC
m
, 100% Production Test with
PR
Input to Output Test Voltage, Method a,
V
x 1.5 = V
IORM
t
= 60 sec.,Partial Discharge < 5 pC
m
, Type and Sample Test with
PR
Max Working Insulation Voltage1,414V
Highest Allowable Over Voltage6000V
2651
2121
peak
peak
Safety Limit Values – Maximum Values Allowed in the
Event of a Failure
Case Temperature150°C
Input Current200mA
Output Power600mW
Insulation Resistance at T
, V
= 500V10
S
IO
9
Ω
FOD8321 — 2.5A Output Current, Gate Drive Optocoupler in Optoplanar
FOD8321 — 2.5A Output Current, Gate Drive Optocoupler in Optoplanar
Absolute Maximum Ratings
(T
= 25ºC unless otherwise specified)
A
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
SymbolParameterValueUnits
T
STG
T
OPR
T
J
T
SOL
I
F(AVG)
F
V
R
I
O(PEAK)
V
DD
V
O(PEAK)
, t
t
R(IN)
F(IN)
PD
I
PD
O
Notes:
1. Maximum pulse width = 10µs, maximum duty cycle = 0.2%.
2.
No derating required across operating temperature range.
3.
Derate linearly from 25°C at a rate of 5.2mW/°C
4.
Functional operation under these conditions is not implied. Permanent damage may occur if the device is subjected
to conditions outside these ratings.
Storage Temperature
Operating Temperature
Junction Temperature
Lead Solder Temperature (Refer to Reflow Temperature
Profile)
Average Input Current
Operating Frequency
Reverse Input Voltage
Peak Output Current
(1)
Supply Voltage
Peak Output Voltage
Input Signal Rise and Fall Time
Input Power Dissipation
Output Power Dissipation
(2)(4)
(3)(4)
-40 to +125°C
-40 to +100°C
-40 to +125°C
260 for 10 sec°C
25mA
50kHz
5.0V
3.0A
0 to 35V
0 to V
DD
V
500ns
45mW
500mW
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Apply over all recommended conditions, typical value is measured at VDD = 30V, VSS = Ground, TA = 25°C unless
otherwise specified.
SymbolParameterConditionsMin.Typ.Max.UnitsFigure
t
PHL
t
PLH
PWDPulse Width Distortion
PDD
(Skew)
t
t
t
ULVO ON
t
ULVO OFF
|CMH|Common Mode Transient
|CML|Common Mode Transient
Propagation Delay Time to
Logic Low Output
Propagation Delay Time to
Logic High Output
|t
– t
PHL
PLH
Propagation Delay Difference
Between Any Two Parts
Output Rise Time
R
(10% to 90%)
Output Fall Time
F
(90% to 10%)
ULVO Turn On DelayIF = 10mA, VO > 5V0.8µs
ULVO Turn Off DelayIF = 10mA, VO < 5V0.4µs
Immunity at Output High
Immunity at Output Low
(9)
(10)
(11)
|
(12)
IF = 10mA to 16mA, Rg = 10Ω,
Cg =10nF, f = 10kHz,
Duty Cycle = 50%
TA = 25°C, VDD = 30V,
IF = 10 to 16mA, VCM = 2000V
TA = 25°C, VDD = 30V, VF = 0V,
VCM = 2000V
(14)
100285500ns10, 11,
100260500ns10, 11,
25300ns
-350350
60ns27
60ns27
2050kV/µs28
(13)
2050kV/µs28
12, 13,
14, 27
12, 13,
14, 27
FOD8321 — 2.5A Output Current, Gate Drive Optocoupler in Optoplanar
Notes:
9. t
10. t
11. PWD is defined as | t
12. The difference between t
propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level of the
PHL
falling edge of the V
propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level of the
PLH
rising edge of the V
signal.
O
signal.
O
PHL
– t
| for any given device.
PLH
PHL
and t
between any two FOD8321 parts under same operating conditions, with equal
PLH
loads.
13. Common mode transient immunity at output high is the maximum tolerable negative dVcm/dt on the trailing edge of
the common mode impulse signal, Vcm, to assure that the output will remain high (i.e. V
> 15.0V).
O
14. Common mode transient immunity at output low is the maximum tolerable positive dVcm/dt on the leading edge of
the common pulse signal, Vcm, to assure that the output will remain low (i.e. V