FOD2200 — Low Input Current Logic Gate Optocouplers
August 2010
FOD2200
Low Input Current Logic Gate Optocouplers
Features
■
1kV/µs minimum common mode rejection
Compatible with LSTTL, TTL, and CMOS logic
■
■
Wide V
2.5Mbd guaranteed over temperature
■
■
Low input current (1.6mA)
Three state output (no pullup resistor required)
■
■
Guaranteed performance from 0°C to 85°C
■
Hysteresis
Safety and regulatory approved
■
– UL1577, 5000 V
range (4.5V to 20V)
CC
for 1 min.
RMS
– IEC60747-5-2
■
>8.0mm clearance and creepage distance
(option ‘T’ or ‘TS’)
■
1,414V Peak Working Insulation Voltage (V
Applications
■
Isolation of high speed logic systems
Computer peripheral interfaces
■
■
Microprocessor system interfaces
Ground loop elimination
■
■
Pulse transformer replacement
Isolated bus driver
■
■
High speed line receiver
IORM
Description
The FOD2200 is an optically coupled logic gate that
combine an AlGaAs LED and an integrated high gain
photo detector. The detector has a three state output
stage and has a detector threshold with hysteresis. The
three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. The hysteresis provides differential mode noise immunity and
eliminates the potential for output signal chatter.
The Electrical and Switching Characteristics of the
FOD2200 are guaranteed over the temperature range of
0°C to 85°C and a V
wide V
range allow compatibility with TTL, LSTTL, and
CC
CMOS logic and result in lower power consumption
compared to other high speed opto-couplers. Logic
)
signals are transmitted with a maximum propagation
delay of 300ns. The FOD2200 is useful for isolating high
speed logic interfaces, buffering of input and output
lines, and implementing isolated line receivers in high
noise environments.
Truth Table
LEDEnableOutput
OnHZ
OffHZ
OnLH
OffLL
range of 4.5V to 20V. Low I
CC
(Positive Logic)
and
F
Functional Block Diagram and Schematic Package Outlines
As per IEC 60747-5-2. This optocoupler is suitable for “safe electrical insulation” only within the safety limit data.
Compliance with the safety ratings shall be ensured by means of protective circuits.
SymbolParameter Min.Typ.Max.Unit
Climatic Classification 40/85/21Pollution Degree (DIN VDE 0110/1.89)2
CTIComparative Tracking Index175
V
PR
V
IORM
V
IOTM
External Creepage8mm
External Clearance7.4mm
Insulation Thickness0.5mm
T
Case
I
S,INPUT
P
S,OUTPUT
R
IO
Installation Classifications per DIN VDE 0110/1.89 Table 1
For Rated Mains Voltage < 150VrmsI–IV
For Rated Mains Voltage < 300VrmsI–IV
For Rated Mains Voltage < 450VrmsI–III
For Rated Mains Voltage < 600VrmsI–III
For Rated Mains Voltage < 1000Vrms (Option T, TS)I–III
Input to Output Test Voltage, Method b,
V
x 1.875 = V
IORM
, 100% Production Test with
PR
2651
tm = 1 sec., Partial Discharge < 5pC
Input to Output Test Voltage, Method a,
V
IORM
x 1.5 = V
, Type and Sample Test with
PR
2121
tm = 60 sec.,Partial Discharge < 5 pC
Max Working Insulation Voltage1,414V
Highest Allowable Over Voltage6000V
External Clearance (for Option T or TS - 0.4” Lead Spacing)10.16mm
Safety Limit Values – Maximum Values Allowed in the
Event of a Failure
Case Temperature150°C
Input Current10mA
Output Power (Duty Factor ≤ 2.7%)150mW
Insulation Resistance at T
, V
= 500V10
S
IO
9
Ω
FOD2200 — Low Input Current Logic Gate Optocouplers
FOD2200 — Low Input Current Logic Gate Optocouplers
Absolute Maximum Ratings
(T
= 25°C unless otherwise specified)
A
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
SymbolParameterValueUnits
T
STG
T
OPR
T
SOL
EMITTER
I
F (PK)
I
F
V
P
DETECTOR
V
CC
I
O
V
V
P
Storage Temperature-40 to +125°C
Operating Temperature-40 to +85°C
Lead Solder Temperature (1.6mm below seating plane)260 for 10 sec°C
Peak Transient Input Current (≤1µs PW, 300pps)1.0A
Average Forward Input Current10mA
Reverse Input Voltage5.0V
R
Output Power Dissipation (No derating required up to 85°C)45mW
D
Supply Voltage0 to 20V
Average Output Current25mA
Three State Enable Voltage-0.5 to 20V
E
Output Voltage-0.5 to 20V
O
Output Power Dissipation (No derating required up to 85°C)150mW
D
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
SymbolParameterMin.Max.Units
I
F(ON)
I
F(OFF)
V
CC
V
EL
V
EH
T
A
NFan Out (TTL Load)4
*The initial switching threshold is 1.6mA or less. It is recommended that 2.2mA be used to permit at least a 20%
CTR degradation guardband.
Withstand Insulation Test Voltage RH < 50%, TA = 25°C, t = 1 min.
ISO
Resistance (Input to Output)V
I-O
Capacitance (Input to Output)V
I-O
= 25°C, VCC = 5V, I
A
= 500 VDC
I-O
= 0V, f = 1MHz
I-O
= 3mA unless otherwise stated.
F(ON)
(9)
(9)
Notes:
1. The V
supply to each optoisolator must be bypassed by a 0.1µF capacitor or larger. This can be either a ceramic
CC
or solid tantalum capacitor with good high frequency characteristic and should be connected as close as possible
to the package V
2. t
– Propagation delay is measured from the 50% level on the LOW to HIGH transition of the input current pulse
PLH
and GND pins of each device.
CC
to the 1.3V level on the LOW to HIGH transition of the output voltage pulse.
3. t
– Propagation delay is measured from the 50% level on the HIGH to LOW transition of the input current pulse
PHL
to the 1.3V level on the HIGH to LOW transition of the output voltage pulse.
4. When the peaking capacitor is omitted, propagation delay times may increase by 100ns.
– Rise time is measured from the 10% to the 90% levels on the LOW to HIGH transition of the output pulse.
5. t
r
– Fall time is measured from the 90% to the 10% levels on the HIGH to LOW transition of the output pulse.
6. t
f
7. CM
8. CM
– The maximum tolerable rate of fall of the common mode voltage to ensure the output will remain in the high
H
state (i.e., V
– The maximum tolerable rate of rise of the common mode voltage to ensure the output will remain in the low
L
state (i.e., V
OUT
OUT
> 2.0V).
< 0.8V).
9. Device considered a two-terminal device: Pins 1, 2, 3 and 4 shorted together, and Pins 5, 6, 7 and 8 shorted together.
10. Duration of output short circuit time should not exceed 10ms.