Fairchild FM24C04U, FM24C05U service manual

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FM24C04U/05U – 4K-Bit Standard 2-Wire Bus
Interface Serial EEPROM

FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM

August 2000

General Description

The FM24C04U/05U devices are 4096 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci­fications in the Standard IIC 2-wire protocol. They are designed to
minimize device pin count and simplify PC board layout require­ments.

The upper half (upper 2Kbit) of the memory of the FM24C05U can
be write protected by connecting the WP pin to VCC. This section of
memory then becomes unalterable unless WP is switched to VSS.

This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the FM24C32 or FM24C65 datasheets for more informa­tion.)

Fairchild EEPROMs are designed and tested for applications requir­ing high endurance, high reliability and low power consumption.

Block Diagram

V

CC

V

SS

WP

SDA

SCL

START

STOP

LOGIC

SLAVE ADDRESS

REGISTER &

COMPARATOR

CONTROL

LOGIC

Features

■ Extended operating voltage 2.7V – 5.5V

■ 400 KHz clock frequency (F) at 2.7V - 5.5V

■ 200µA active current typical

10µA standby current typical
1µA standby current typical (L)

0.1µA standby current typical (LZ)

■ IIC compatible interface
– Provides bi-directional data transfer protocol

■ Sixteen byte page write mode
– Minimizes total write time per byte

■ Self timed write cycle
Typical write cycle time of 6ms

■ Hardware Write Protect for upper half (FM24C05U only)

■ Endurance: 1,000,000 data changes

■ Data retention greater than 40 years

■ Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP

■ Available in three temperature ranges

- Commercial: 0° to +70°C

- Extended (E): -40° to +85C

- Automotive (V): -40° to +125°C

H.V. GENERATION

TIMING &CONTROL

XDEC

E2PROM

ARRAY

A2
A1

© 2000 Fairchild Semiconductor International

FM24C04U/05U Rev. A.3

R/W

WORD
ADDRESS
COUNTER

D

IN

YDEC

CK

DATA REGISTER

1

D

OUT

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Connection Diagrams

Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)

FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Pin Names

A1,A2 Device Address Inputs

V

SS

SDA Serial Data I/O

SCL Serial Clock Input

NC No Connection

V

CC

NC

A1

1

2

V

8

CC

NC

7

24C04

A2

3

V

SS

4

SCL

6

SDA

5

See Package Number N08E, M08A and MTC08

Ground

Power Supply

Dual-in-Line Package (N), SO Package (M8) and TSSOP Package (MT8)

Pin Names

A1,A2 Device Address Inputs

V

SS

SDA Serial Data I/O

SCL Serial Clock input

WP Write Protect

V

CC

NC No Connection

NC

A1

1

2

V

8

CC

WP

7

24C05

A2

3

V

SS

4

SCL

6

SDA

5

See Package Number N08E, M08A and MTC08

Ground

Power Supply

FM24C04U/05U Rev. A.3

2

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Ordering Information

FM 24 C XX U F LZ E XXX Letter Description

FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Package N 8-pin DIP

Temp. Range Blank 0 to 70°C

Voltage Operating Range Blank 4.5V to 5.5V

SCL Clock Frequency Blank 100KHz

Process U Ultralite CS100UL

Density 04 4K

Interface 24 IIC

M8 8-pin SOIC
MT8 8-pin TSSOP

V -40 to +125°C
E -40 to +85°C

L 2.7V to 5.5V
LZ 2.7V to 5.5V and

<1µA Standby Current

F 400KHz

05 4K with Write Protect

C CMOS Technology

FM Fairchild Non-Volatile

Memory

FM24C04U/05U Rev. A.3

3

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Product Specifications

FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Absolute Maximum Ratings

Ambient Storage Temperature –65°C to +150°C

All Input or Output Voltages

with Respect to Ground –0.3V to 6.5V

Lead Temperature

(Soldering, 10 seconds) +300°C

ESD Rating 2000V min.

Operating Conditions

Ambient Operating Temperature

FM24C04U/05U 0°C to +70°C
FM24C04UE/05UE -40°C to +85°C
FM24C04UV/05UV -40°C to +125°C

Positive Power Supply

FM24C04U/05U 4.5V to 5.5V
FM24C04UL/05UL 2.7V to 5.5V
FM24C04ULZ/05ULZ 2.7V to 5.5V

DC Electrical Characteristics (2.7V to 5.5V)

Symbol Parameter Test Conditions Limits Units

Min Typ Max

(Note 1)

I

CCA

I

SB

(Note 3) or V

I

LI

I

LO

V

IL

V

IH

V

OL

Active Power Supply Current f

= 400 KHz ("F" version) 0.2 1.0 mA

SCL

f

= 100 KHz

SCL

Standby Current VIN = GND VCC = 2.7V - 5.5V 10 50 µA

CC

VCC = 2.7V - 5.5V (L) 1 10 µA
VCC = 2.7V - 4.5V (LZ) 0.1 1 µA

Input Leakage Current VIN = GND to V

Output Leakage Current V

= GND to V

OUT

CC

CC

Input Low Voltage –0.3 V

0.1 1 µA

0.1 1 µA

x 0.3 V

CC

Input High Voltage VCC x 0.7 VCC + 0.5 V

Output Low Voltage IOL = 3 mA 0.4 V

Capacitance T

= +25°C, f = 100/400 KHz, VCC = 5V (Note 2)

A

Symbol Test Conditions Max Units

C

I/O

C

IN

Note 1: Typical values are TA = 25°C and nominal supply voltage of 5V for 4.5V-5.5V operation and at 3V for 2.7V-4.5V operation.

Note 2: This parameter is periodically sampled and not 100% tested.

Note 3: The "L" and "LZ" versions can be operated in the 2.7V to 5.5V VCC range. However, for a standby current (ISB) of 1µA, the VCC should be within 2.7V to 4.5V.

Input/Output Capacitance (SDA) V

= 0V 8 pF

I/O

Input Capacitance (A0, A1, A2, SCL) VIN = 0V 6 pF

FM24C04U/05U Rev. A.3

4

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FM24C04U/05U – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM

AC Test Conditions

Input Pulse Levels VCC x 0.1 to VCC x 0.9

Input Rise and Fall Times 10 ns

AC Testing Input/Output Waveforms

0.9VCC

0.1VCC

Input & Output Timing Levels VCC x 0.3 to VCC x 0.7

Output Load 1 TTL Gate and C

= 100 pF

L

Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 5.5V)

Symbol Parameter 100 KHz 400 KHz Units

Min Max Min Max

f

SCL

T

I

t

AA

t

BUF

t

HD:STA

t

LOW

t

HIGH

t

SU:STA

t

HD:DAT

t

SU:DAT

t

R

t

F

t

SU:STO

t

DH

t

WR

(Note 4) 4.5V to 5.5V V

SCL Clock Frequency 100 400 KHz

Noise Suppression Time Constant at
SCL, SDA Inputs (Minimum V

IN

100 50 ns

Pulse width)

SCL Low to SDA Data Out Valid 0.3 3.5 0.1 0.9 µs

Time the Bus Must Be Free before 4.7 1.3 µs
a New Transmission Can Start

Start Condition Hold Time 4.0 0.6 µs

Clock Low Period 4.7 1.5 µs

Clock High Period 4.0 0.6 µs

Start Condition Setup Time 4.7 0.6 µs
(for a Repeated Start Condition)

Data in Hold Time 0 0 ns

Data in Setup Time 250 100 ns

SDA and SCL Rise Time 1 0.3 µs

SDA and SCL Fall Time 300 300 ns

Stop Condition Setup Time 4.7 0.6 µs

Data Out Hold Time 300 50 ns

Write Cycle Time

10 10 ms
15 15

2.7V to 4.5V V

CC

CC

0.7VCC

0.3VCC

Note 4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the
FM24C04U/05U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer
"Write Cycle Timing" diagram.

Bus Timing

t

LOW

t

R

t

t

SU:DAT

t

DH

SU:STO

t

BUF

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FM24C04U/05U Rev. A.3

SCL

SDA

SDA

OUT

t

F

t

t

LOW

t

SU:STA

IN

t

HD:STA

HIGH

t

HD:DAT

t

AA

5