Fairchild FDT459N service manual
March 1998
FDT459N
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
These N-Channel enhancement mode power field effect
transistors are produced using Fairchild's proprietary, high
cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state resistance,
provide superior switching performance. These products are
well suited to low voltage, low current applications such as
notebook computer power management, battery powered
circuits, and DC motor control.
SuperSOTTM-3
SuperSOTTM-6
G
SuperSOTTM-8
D
D S
6.5 A, 30 V. R
R
High density cell design for extremely low R
= 0.035Ω @ VGS = 10 V
DS(ON)
= 0.055 Ω @ VGS = 4.5 V.
DS(ON)
.
DS(ON)
High power and current handling capability in a widely used
surface mount package.
SO-8
SOT-223
SOIC-16
D
G
S
Absolute Maximum Ratings T
= 25oC unless otherwise noted
A
Symbol Parameter FDT459N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage - Continuous ±20 V
Maximum Drain Current - Continuous (Note 1a) 6.5 A
- Pulsed 20
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 3 W
(Note 1b)
(Note 1c)
Operating and Storage Temperature Range -55 to 150 °C
STG
1.3
1.1
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 42 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 12 °C/W
* Order option J23Z for cropped center drain lead.
© 1998 Fairchild Semiconductor Corporation
FDT459NRev.C
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
ID = 250 µA, Referenced to 25 o C
VDS = 24 V, V
GS
= 0 V
33
1 µA
mV/ oC
TJ =55°C 10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward
VGS = 20 V, VDS = 0 V
Gate - Body Leakage, Reverse VGS = -20 V, VDS = 0 V -100 nA
100 nA
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage
Gate Threshold Voltage Temp.Coefficient ID = 250 µA, Referenced to 25 oC -4.2 mV/ oC
/∆T
J
VDS = VGS, ID = 250 µA
Static Drain-Source On-Resistance VGS = 10 V, ID = 6.5 A 0.031 0.035
TJ =125°C
1 1.6 2 V
Ω
0.044 0.06
VGS = 4.5 V, ID = 5.5 A 0.046 0.055
I
D(ON)
g
On-State Drain Current
FS
Forward Transconductance VDS = 10 V, ID = 6.5 A 16 S
VGS = 10 V, VDS = 5 V
20 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 210 pF
VDS = 15 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 70 pF
365 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 8.2 16 ns
VDD = 15 V, ID = 1 A,
VGS = 10 V, R
GEN
= 6 Ω
Turn - Off Delay Time 6 12 ns
Turn - Off Fall Time 16 26 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 2.2 nC
Gate-Drain Charge 3 nC
VDS = 10 V, ID = 6.5 A,
VGS = 10 V
5.2 11 ns
12 17 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
design while R
Typical R
Maximum Continuous Drain-Source Diode Forward Current 2.5 A
Drain-Source Diode Forward Voltage
is determined by the user's board design.
CA
θ
using the board layouts shown below on FR-4 PCB in a still air environment:
JA
θ
VGS = 0 V, IS = 2.5 A
(Note 2)
0.8 1.2 V
is guaranteed by
JC
θ
a. 42oC/W when mounted on a 1 in2 pad of
2oz Cu.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
b. 95oC/W when mounted on a 0.066 in
pad of 2oz Cu.
2
c. 110oC/W when mounted on a 0.00123
2
in
pad of 2oz Cu.
FDT459NRev.C
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