Fairchild FDS8960C service manual

November 2005

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FDS8960C

D

Dual N & P-Channel PowerTrench® MOSFET

l N

General Description

These dual N- and P-Channel enhancement mode
power field effect transistors are produced using
Fairchild Semiconductor’s advanced PowerTrench
process that has been especially tailored to minimize
on-state ressitance and yet maintain superior switching
performance.

These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.

D2

D

D2

D

D1

D

D1

D

SO-8

Pin 1

SO-8

S1

Absolute Maximum Ratings T

G2

S2

G

G1

S

S

S

= 25°C unless otherwise noted

A

Symbol Parameter Q1 Q2 Units

V

Drain-Source Voltage 35 –35 V

DSS

V

DS(Avalanche)

V

GSS

ID Drain Current - Continuous (Note 1a) 7 –5 A

- Pulsed 20 –20
PD Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6

TJ, T

Drain-Source Avalanche Voltage (maximum) (Note 3) 40 –40 V

Gate-Source Voltage

Operating and Storage Junction Temperature Range –55 to +150

STG

Thermal Characteristics

R

θJA

R

θJC

Thermal Resistance, Junction-to-Ambient (Note 1a) 78
Thermal Resistance, Junction-to-Case (Note 1) 40

Package Marking and Ordering Information

Device Marking Device Reel Size Tape width Quantity

FDS8960C FDS8960C 13” 12mm 2500 units

©2005 Fairchild Semiconductor Corporation
FDS8960C Rev C1(W)

Features

• Q1: N-Channel

7.0A, 35V R
R

• Q2: P-Channel
–5A, –35V R

R

• Fast switching speed

• RoHS compliant

5
6
7
8

±20 ±25

(Note 1b)
(Note 1c)

P-

= 0.024Ω @ VGS = 10V

DS(on)

= 0.032Ω @ VGS = 4.5V

DS(on)

h
nn

= 0.053Ω @ VGS = –10V

DS(on)

= 0.087Ω @ VGS = –4.5V

DS(on)

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rTr
n

Q2

Q1

4
3
2
1

V

1

0.9

°C

°C/W
°C/W

www.fairchildsemi.com

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Electrical Characteristics T

= 25°C unless otherwise noted

A

Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Avalanche Ratings

E

Drain-Source Avalanche

AS

I

Drain-Source Avalanche

AS

Energy (Single Pulse)

Current

VDD = 35 V, ID = 7 A, L = 1 mH Q1 24.5 mJ

= –35 V, ID =–5 A, L = 1 mH Q2 12.5 mJ

V

DD

Q1

Q2

7

–5

A

Off Characteristics

Q1

BV

Drain-Source Breakdown

DSS

ΔBVDSS
ΔT

I

Zero Gate Voltage Drain

DSS

I

GSSF

I

GSSR

I

GSSR

I

GSSF

Voltage
Breakdown Voltage

Temperature Coefficient

J

Current

Gate-Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate-Body Leakage, Reverse VGS = –20 V, VDS = 0 V
Gate-Body Leakage, Forward VGS = 25 V, VDS = 0 V 100 nA
Gate-Body Leakage, Reverse VGS = –25 V, VDS = 0 V

= 0 V, ID = 250 μA

V

GS

= 0 V, ID = –250 μA

V

GS

= 250 μA, Referenced to 25°C

I

D

= –250 µA, Referenced to 25°C

I

D

VDS = 28 V, VGS = 0 V

= –28 V, VGS = 0 V

V

DS

Q2

–35

Q1
Q2

Q1
Q2
Q1

Q2

35

V

31

–40

1

–100 nA

–100 nA

–1

mV/°C

μA

On Characteristics (Note 2)

V

Gate Threshold Voltage

GS(th)

ΔVGS(th)
ΔTJ

R

DS(on)

gFS Forward Transconductance VDS = 5 V, ID = 7 A

Gate Threshold Voltage
Temperature Coefficient

Static Drain-Source

On-Resistance

= VGS, ID = 250 μA

V

DS

= VGS, ID = –250 µA

V

DS

I

= 250 μA, Referenced to 25°C

D

= –250 µA, Referenced to 25°C

I

D

VGS = 10 V, ID = 7 A

= 4.5 V, ID = 6 A

V

GS

= 10 V, ID = 7 A, TJ = 125°C

V

GS

= –10 V, ID = –5 A

V

GS

= –4.5 V, ID = –4 A

V

GS

= –10 V, ID = –5 A, TJ = 125°C

V

GS

= –5 V, ID =–5 A

V

DS

Q1
Q2 1 –1 2 –1.8 3 –3

Q1
Q2

Q1 20

Q2 44

Q1
Q2

–5 4

25
29

70
61

23 9 S

24
32
37

53
87
79

V

mV/°C

mΩ

Dynamic Characteristics

C

Input Capacitance Q1

iss

C

Output Capacitance Q1

oss

C

Reverse Transfer Capacitance

rss

RG Gate Resistance f = 1.0 MHz

Q1

= 15 V, VGS = 0 V, f = 1.0 MHz

V

DS

Q2

= –15 V, VGS = 0 V, f = 1.0 MHz

V

DS

Q2
Q2

Q1
Q2
Q1
Q2

570

540

126

113

52

60

2 6

pF
pF
pF

Ω

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P­h

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FDS8960C Rev C1(W) www.fairchildsemi.com

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Electrical Characteristics (continued) T

Symbol

Parameter

Test Conditions

= 25°C unless otherwise noted

A

Type Min Typ Max Units

Switching Characteristics (Note 2)

t

Turn-On Delay Time

d(on)

tr Turn-On Rise Time
t

Turn-Off Delay Time

d(off)

tf Turn-Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge

Q1

= 15 V, ID = 1 A,

V

DD

= 10V, R

V

GS

Q2

= –15 V, ID = -1 A,

V

DD

= –10V, R

V

GS

Q1

= 15 V, ID = 7 A, VGS = 5 V

V

DS

Q2

= –15 V, ID = –5 A,VGS = –5 V

V

DS

GEN

GEN

= 6 Ω

= 6 Ω

Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2

8

12

5

16

23

20

3 5 6

5.5

5.7

1.8

1.8

1.8 2 nC

Drain–Source Diode Characteristics

IS Maximum Continuous Drain-Source Diode Forward Current Q1
VSD Drain-Source Diode Forward
trr Diode Reverse Recovery
Qrr Diode Reverse Recovery

Notes:

1. R

θJA

the drain pins. R

Voltage
Time
Charge

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of

is guaranteed by design while R

θJC

VGS = 0 V, IS = 1.3 A (Note 2)
VGS = 0 V, IS = –1.3 A (Note 2)
Q1

= 7 A, diF/dt = 100 A/µs

I

F

Q2

= -5 A, diF/dt = 100 A/µs

I

F

is determined by the user's board design.

θCA

Q2
Q1
Q2
Q1
Q2
Q1
Q2

1.3

0.8
–0.8

20
10 5 nC

–1.3
–1.2

17

16
22
10
29
37
32

10

7.7 8 nC

1.2

ns
ns
ns
ns

nC

A
V

nS

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FET

a) 78°C/W when

mounted on a

2

0.5 in

pad of 2 oz

copper

Scale 1 : 1 on letter size paper

2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%

3. BV(avalanche) Single-Pulse rating is guaranteed by design if device is operated within the UIS SOA boundary of the device.

FDS8960C Rev C1(W) www.fairchildsemi.com

b) 125°C/W when

mounted on a .02 in2
pad of 2 oz copper

c) 135°C/W when mounted on a

minimum pad.