Q1-N-Channel: 30 V, 6.4 A, 26 mΩ Q2-P-Channel: -30 V, -4.5 A, 51 mΩ
FDS8958B Dual N & P-Channel PowerTrench
December 2008
Features
Q1: N-Channel
Max r
Max r
Q2: P-Channel
Max r
Max r
HBM ESD protection level > 3.5 kV (Note 3)
RoHS Compliant
= 26 mΩ at VGS = 10 V, ID = 6.4 A
DS(on)
= 39 mΩ at VGS = 4.5 V, ID = 5.2 A
DS(on)
= 51 mΩ at VGS = -10 V, ID = -4.5 A
DS(on)
= 80 mΩ at VGS = -4.5 V, ID = -3.3 A
DS(on)
D2
D2
D1
D1
Pin 1
S1
SO-8
G1
S2
G2
General Description
These dual N- and P-Channel enhancement mode power field
effect transistors are produced using Fairchild Semiconductor's
advanced PowerTrench
tailored to minimize on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and battery
powered applications where low in-line power loss and fast
switching are required.
®
process that has been especially
Application
DC-DC Conversion
BLU and motor drive inverter
D2
D2
D1
D1
5
Q2
6
Q1Q2Q1Q2Q1
7
8
G2
4
S2
3
G1
2
S1
1
®
MOSFET
MOSFET Maximum RatingsT
SymbolParameterQ1Q2Units
V
DS
V
GS
I
D
P
D
E
AS
, T
T
J
STG
Drain to Source Voltage30-30V
Gate to Source Voltage±20±25V
Drain Current - Continuous TA = 25 °C6.4-4.5
- Pulsed30-30
Power Dissipation for Dual Operation 2.0
T
Single Pulse Avalanche Energy (Note 4)185mJ
Operating and Storage Junction Temperature Range-55 to +150°C
= 25 °C unless otherwise noted
C
A
A
= 25 °C (Note 1a)1.6
= 25 °C (Note 1b)0.9
A
WPower Dissipation for Single Operation T
Thermal Characteristics
R
θJC
R
θJA
Thermal Resistance, Junction to Case (Note 1)40
Thermal Resistance, Junction to Ambient (Note 1a)78