Fairchild FDS8958A Service Manual

FDS8958A
Dual N & P-Channel PowerTrench

FDS8958A
January 2002
General Description
These dual N- and P-Channel enhancement mode power field effect transistors are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state ressitance and yet maintain superior switching performance.
These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required.
D2
D
D2
D
D1
D
D1
D
SO-8
Pin 1
SO-8
S1
Absolute Maximum Ratings T
G2
S2
G
G1
S
S
S
= 25°C unless otherwise noted
A
Features
Q1: N-Channel
7.0A, 30V R
R
Q2: P-Channel
-5A, -30V R
R
Fast switching speed
High power and handling capability in a widely
used surface mount package
5
6
7
8
= 0.028 @ VGS = 10V
DS(on)
= 0.040 @ VGS = 4.5V
DS(on)
= 0.052 @ VGS = -10V
DS(on)
= 0.080 @ VGS = -4.5V
DS(on)
Q2
Q1
4
3
2
1
Symbol Parameter Q1 Q2 Units
V
Drain-Source Voltage 30 30 V
DSS
V
Gate-Source Voltage
GSS
ID Drain Current - Continuous (Note 1a) 7 -5 A
- Pulsed 20 -20
PD Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
TJ, T
STG
Operating and Storage Junction Temperature Range -55 to +150
(Note 1b)
(Note 1c)
±20 ±20
1
0.9
V
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a) 78
(Note 1) 40
°C/W
°C/W
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS8958A FDS8958A 13” 12mm 2500 units
2002 Fairchild Sem iconductor Corporation
FDS8958A Rev D1(W )
FDS8958A
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
Q1
BV
Drain-Source Breakdown
DSS
Voltage
BVDSS T
I
Zero Gate Voltage Drain
DSS
Breakdown Voltage Temperature Coefficient
J
Current
I
Gate-Body Leakage, Forward VGS = 20 V, VDS = 0 V All 100 nA
GSSF
I
Gate-Body Leakage, Reverse VGS = -20 V, VDS = 0 V All -100 nA
GSSR
V
= 0 V, ID = 250 µA
GS
= 0 V, ID = -250 µA
V
GS
= 250 µA, Referenced to 25°C
I
D
= -250 µA, Referenced to 25°C
I
D
VDS = 24 V, VGS = 0 V
= -24 V, VGS = 0 V
V
DS
Q2 Q1
Q2 Q1
Q2
30
-30
V
25
mV/°C
-22
1
-1
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
VGS(th)TJ
R
DS(on)
Gate Threshold Voltage Temperature Coefficient
Static Drain-Source
On-Resistance
I
On-State Drain Current VGS = 10 V, VDS = 5 V
D(on)
V
= VGS, ID = 250 µA
DS
= VGS, ID = -250 µA
V
DS
= 250 µA, Referenced to 25°C
I
D
= -250 µA, Referenced to 25°C
I
D
VGS = 10 V, ID = 7 A
= 10 V, ID = 7 A, TJ = 125°C
V
GS
= 4.5 V, ID = 6 A
V
GS
V
= -10 V, ID = -5 A
GS
= -10 V, ID = -5 A, TJ = 125°C
V
GS
= -4.5 V, ID = -4 A
V
GS
V
= -10 V, VDS = -5 V
GS
gFS Forward Transconductance VDS = 5 V, ID = 7 A
= -5 V, ID =-5 A
V
DS
Q1 Q2 1 -1
Q1 Q2
Q1 21
Q2 41
Q1 Q2 Q1 Q2
1.6
-1.7 3 -3
-4.3 4
32 27
58 58
20
A
-20 19
11
mV/°C
28
m 42 40
52 78 80
S
Dynamic Characteristics
C
Input Capacitance Q1
iss
C
Output Capacitance Q1
oss
C
Reverse Transfer Capacitance
rss
Q1
= 10 V, VGS = 0 V, f = 1.0 MHz
V
DS
Q2
= -10 V, VGS = 0 V, f = 1.0 MHz
V
DS
Q2
Q2 Q1 Q2
789
690
173
306
66
77
pF
pF
pF
µA
V
FDS8958A Rev D1(W )
FDS8958A
Electrical Characteristics (continued) T
Symbol
Parameter
Test Conditions
= 25°C unless otherwise noted
A
Type Min Typ Max Units
Switching Characteristics (Note 2)
t
Turn-On Delay Time
d(on)
tr Turn-On Rise Time
t
Turn-Off Delay Time
d(off)
tf Turn-Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
Q1 VDD = 10 V, ID = 1 A, V
= 10V, R
GS
GEN
= 6
Q2
= -10 V, ID = -1 A,
V
DD
= -10V, R
V
GS
GEN
= 6
Q1
= 15 V, ID = 7 A, VGS = 10 V
V
DS
Q2 V
= -15 V, ID = -5 A,VGS = -10 V
DS
Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2
2.2
6.7
13.4
7.5
9.7
19.8
19.4
21.3
35.6
11.8
3.7
12.3
22.2
16
14
2.5
2.2
2.1
1.9
4.4
7.4
Drain–Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain-Source Diode Forward Current Q1
Q2
VSD Drain-Source Diode Forward
Voltage
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
is guaranteed by design while R
θJC
VGS = 0 V, IS = 1.3 A (Note 2) VGS = 0 V, IS = -1.3 A (Note 2)
is determined by the user's board design.
θCA
Q1 Q2
1.3
-1.3
0.74
-0.76
1.2
-1.2
ns
15
ns
ns
ns
26
nC
23
nC
nC
A
V
a) 78°/W when
mounted on a
0.5 in2 pad of 2 oz copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
b) 125°/W when
mounted on a .02 in2 pad of 2 oz copper
c) 135°/W when mounted on a
mini mum pa d.
FDS8958A Rev D1(W )
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