Fairchild FDS89161LZ service manual
FDS89161LZ
G2
S1
G1
S2
D2
D2
D1
D1
Pin 1
SO-8
D1
D1
D2
D2
S2
S1
G1
G2
4
3
2
1
5
6
7
8
Q2
Q1
Dual N-Channel PowerTrench® MOSFET
100 V, 2.7 A, 105 mΩ
Features
Max r
Max r
High performance trench technology for extremely low r
High power and current handling capability in a widely used
surface mount package
CDM ESD protection level > 2KV typical (Note 4)
100% UIL Tested
RoHS Compliant
= 105 mΩ at V
DS(on)
= 160 mΩ at V
DS(on)
= 10 V, ID = 2.7 A
GS
= 4.5 V, ID = 2.1 A
GS
DS(on)
General Description
This N-Channel logic Level MOSFETs are produced using
Fairchild Semiconductor‘s advanced Power Trench
that has been special tailored to minimize the on-state
resisitance and yet maintain superior switching performance.
G-S zener has been added to enhance ESD voltage level
Application
DC-DC conversion
June 2011
®
process
.
FDS89161LZ Dual N-Channel PowerTrench
®
MOSFET
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
E
AS
P
D
, T
T
J
STG
Drain to Source Voltage 100 V
Gate to Source Voltage ±20 V
Drain Current -Continuous 2.7
-Pulsed 15
Single Pulse Avalanche Energy (Note 3) 13 mJ
Power Dissipation TC = 25 °C 31
Power Dissipation T
Operating and Storage Junction Temperature Range -55 to +150 °C
= 25 °C unless otherwise noted
A
= 25 °C (Note1a) 1.6
A
A
W
Thermal Characteristics
R
θJC
R
θJA
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDS89161LZ FDS89161LZ SO-8 13 ’’ 12 mm 2500 units
©2011 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FDS89161LZ Rev. C4
Thermal Resistance, Junction to Case (Note 1) 4.0
Thermal Resistance, Junction to Ambient (Note 1a) 78
°C/W
FDS89161LZ Dual N-Channel PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
ΔBV
ΔT
I
DSS
I
GSS
DSS
DSS
J
Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 V
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current VDS = 80 V, V
Gate to Source Leakage Current VGS = ±20 V, V
I
= 250 μA, referenced to 25 °C 68 mV/°C
D
= 0 V 1 μA
GS
= 0 V ±10 μA
DS
On Characteristics
V
GS(th)
ΔV
ΔT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA11.72.2V
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
I
= 250 μA, referenced to 25 °C -6 mV/°C
D
V
= 10 V, ID = 2.7 A 81 105
GS
= 4.5 V, ID = 2.1 A 110 160
GS
= 10 V, ID = 2.7 A, TJ = 125 °C 140 182
V
GS
Forward Transconductance VDS = 10 V, ID = 2.7 A 7.8 S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance 44 58 pF
Reverse Transfer Capacitance 3 4 pF
= 50 V, VGS = 0 V,
V
DS
f = 1MHz
Gate Resistance 0.9 Ω
227 302 pF
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
Q
g(TOT)
g(TOT)
gs
gd
Turn-On Delay Time
Rise Time 1.2 10 ns
Turn-Off Delay Time 9.5 17 ns
= 50 V, ID = 2.7 A,
V
DD
V
= 10 V, R
GS
GEN
= 6 Ω
Fall Time 1.6 10 ns
Total Gate Charge V
Total Gate Charge V
Gate to Source Charge 0.7 nC
= 0 V to 10 V
GS
= 0 V to 5 V 2.1 2.9 nC
GS
V
DD
I
= 2.7 A
D
= 50 V,
Gate to Drain “Miller” Charge 0.7 nC
3.8 10 ns
3.8 5.3 nC
mΩV
®
MOSFET
Drain-Source Diode Characteristics
V
= 0 V, IS = 2.7 A (Note 2) 0.8 1.3
V
SD
t
rr
Q
rr
NOTES:
is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
1. R
θJA
the user's board design.
2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%.
3. Starting TJ = 25 °C, L = 0.3 mH, IAS =25 A, VDD = 27 V, VGS = 10V.
4. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
©2011 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com
FDS89161LZ Rev. C4
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge 20 36 nC
a) 78°C/W when
mounted on a 1 in
pad of 2 oz copper
GS
= 0 V, IS = 2 A (Note 2) 0.8 1.2
V
GS
= 2.7 A, di/dt = 100 A/μs
I
F
2
31 56 ns
is guaranteed by design while R
θJC
b) 135°C/W when
mounted on a
minimun pad
is determined by
θCA
V
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