Fairchild FDS6975 service manual
February 1999
FDS6975
Dual P-Channel, Logic Level, PowerTrenchTM MOSFET
General Description Features
These P-Channel Logic Level MOSFETs are
produced using Fairchild Semiconductor's advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
low gate charge for superior switching performance.
These devices are well suited for notebook computer
applications: load switching and power management,
battery charging circuits, and DC/DC conversion.
-6 A, -30 V. R
R
= 0.032 Ω @ VGS = -10 V,
DS(ON)
= 0.045 Ω @ VGS = -4.5 V.
DS(ON)
Low gate charge (14.5nC typical).
High performance trench technology for extremely low
R
.
DS(ON)
High power and current handling capability.
SOT-23
SuperSOTTM-8
SO-8 SOT-223SuperSOTTM-6
SOIC-16
D2
D2
D1
D1
FDS
6975
G2
S2
G1
1
SO-8
Absolute Maximum Ratings T
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) -6 A
pin
S1
= 25oC unless otherwise noted
A
5
6
7
8
- Pulsed -20
P
D
Power Dissipation for Dual Operation 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
TJ,T
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
4
3
2
1
© 1999 Fairchild Semiconductor Corporation
FDS6975 Rev.C
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, I D = -250 µA -30 V
Breakdown Voltage Temp. Coefficient ID = -250 µA, Referenced to 25 oC -21 mV/oC
/∆T
J
Zero Gate Voltage Drain Current VDS = -24 V, V
= 0 V -1 µA
GS
TJ = 55°C -10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse VGS = -20 V, V
= 0 V -100 nA
DS
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.7 -3 V
Gate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC 4 mV/oC
/∆T
J
Static Drain-Source On-Resistance VGS = -10 V, I D = -6 A 0.025 0.032
Ω
TJ =125°C 0.033 0.051
VGS = -4.5 V, I D = -5 A 0.034 0.045
I
D(ON)
g
FS
On-State Drain Current VGS = -10 V, VDS = -5 V -20 A
Forward Transconductance VDS = -10 V, I D = -6 A 16 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = -15 V, VGS = 0 V,
Output Capacitance 400 pF
f = 1.0 MHz
1540 pF
Reverse Transfer Capacitance 170 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time V
Turn - On Rise Time
= -15 V, I D = -1 A 13 24 ns
DS
V
GEN
= -10 V, R
GEN
= 6 Ω
22 35 ns
Turn - Off Delay Time 47 75 ns
Turn - Off Fall Time 18 30 ns
Total Gate Charge VDS = -10 V, I D = -6 A, 14.5 20 nC
Gate-Source Charge V
= -5 V 4 nC
GS
Gate-Drain Charge 5 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
JA
θ
guaranteed by design while R
Maximum Continuous Drain-Source Diode Forward Current -1.3 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.3 A
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design.
CA
θ
(Note 2) -0.73 -1.2 V
JC
θ
is
a. 78OC/W on a 0.5 in
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
2
b. 125OC/W on a 0.02 in
pad of 2oz copper.
2
c. 135OC/W on a 0.003 in
pad of 2oz copper.
2
FDS6975 Rev.C
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