Fairchild FDS6961A service manual
April 1999
FDS6961A
Dual N-Channel Logic Level PowerTrenchTM MOSFET
General Description Features
These N-Channel Logic Level MOSFETs are
produced using Fairchild Semiconductor's
advanced PowerTrench process that has been
especially tailored to minimize the on-state
resistance and yet maintain superior switching
performance.
These devices are well suited for low voltage
and battery powered applications where low
in-line power loss and fast switching are
required.
3.5 A, 30 V. R
R
= 0.090 Ω @ VGS = 10 V
DS(ON)
= 0.140 Ω @ VGS = 4.5 V.
DS(ON)
Fast switching speed.
Low gate charge (2.1nC typical).
High performance trench technology for extremely low
R
.
DS(ON)
High power and current handling capability.
SOT-23
D1
D1
D2
D2
FDS
6961A
SuperSOTTM-8
SO-8 SOT-223SuperSOTTM-6
5
6
7
4
3
2
SOIC-16
G2
S2
G1
1
SO-8
Absolute Maximum Ratings T
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage ±20 V
Drain Current - Continuous (Note 1a) 3.5 A
pin
S1
= 25oC unless other wise noted
A
8
- Pulsed 14
P
D
Power Dissipation for Single Operation (Note 1) 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
TJ,T
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Operating and Storage Temperature Range -55 to 150 °C
STG
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 40 °C/W
1
© 1999 Fairchild Semiconductor Corporation
FDS6961A Rev.C
Electrical Characteristics ( T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, I D = 250 µA 30 V
Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC 25 mV/oC
/∆T
J
Zero Gate Voltage Drain Current VDS = 24 V, V
= 0 V 1 µA
GS
TJ = 55°C 10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse VGS = -20 V, V
= 0 V -100 nA
DS
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.8 3 V
Gate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC -5 mV/oC
/∆T
J
Static Drain-Source On-Resistance VGS = 10 V, I D = 3.5 A 0.076 0.09
TJ =125°C 0.11 0.155
VGS = 4.5 V, I D = 2.8 A 0.107 0.14
I
D(ON)
g
FS
On-State Drain Current VGS = 10 V, VDS = 5 V 14 A
Forward Transconductance VDS = 15 V, I D = 3.5 A 6 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 15 V, VGS = 0 V,
Output Capacitance 50 pF
f = 1.0 MHz
220 pF
Reverse Transfer Capacitance 20 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time V
Turn - On Rise Time
= 15 V, I D = 1 A 3 6 ns
DS
VGS = 10 V , R
GEN
= 6 Ω
11 22 ns
Turn - Off Delay Time 7 14 ns
Turn - Off Fall Time 3 6 ns
Total Gate Charge VDS = 15 V, I D = 3.5 A, 2.1 4 nC
Gate-Source Charge V
= 5 V 0.8 nC
GS
Gate-Drain Charge 0.7 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
JA
θ
guaranteed by design while R
Maximum Continuous Drain-Source Diode Forward Current 1.3 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design.
CA
θ
(Note 2) 0.73 1.2 V
Ω
is
JC
θ
a. 78OC/W on a 0.5 in
pad of 2oz copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
2
b. 125OC/W on a 0.02 in
pad of 2oz copper.
2
c. 135OC/W on a minimum
mounting pad.
FDS6961A Rev.C
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