Fairchild FDS6930B service manual
FDS6930B
Dual N-Channel Logic Level PowerTrench® MOSFET
FDS6930B Dual N-Channel Logic Level PowerTrench
March 2010
Features
■ 5.5 A, 30 V. R
■ Fast switching speed
■ Low gate charge
■ High performance trench technology for extremely
low R
DS(ON)
■ High power and current handling capability
Absolute Maximum Ratings
= 38 m Ω @ VGS = 10 V
DS(ON)
R
= 50 m Ω @ VGS = 4.5 V
DS(ON)
D1
D1
SO-8
D2
Pin 1
D2
S2
G1
S1
TA= 25°C unless otherwise noted
G2
General Description
These N-Channel Logic Level MOSFETs are produced using
Fairchild Semiconductor’s advanced PowerTrench process that
has been especially tailored to minimize the on-state resistance
and yet maintain superior switching performance.
These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required.
45
36
27
18
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
T
, T
J
STG
Thermal Characteristics
R
θJA
R
θJC
Drain-Source Voltage 30 V
Gate-Source Voltage
Drain Current – Continuous (Note 1a) 5.5 A
– Pulsed 20
Power Dissipation for Dual Operation (Note 1) 2 W
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b) 1
(Note 1c) 0.9
Operating and Storage Junction Temperature Range –55 to 150
Thermal Resistance, Junction-to-Ambient (Note 1a) 78
Thermal Resistance, Junction-to-Case (Note 1) 40
± 20 V
°C
°C/W
°C/W
®
MOSFET
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS6930B FDS6930B 13" 12mm 2500 units
©2010 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FDS6930B Rev. A1
FDS6930B Dual N-Channel Logic Level PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BVDSS
∆T
J
I
DSS
I
GSS
On Characteristics
V
GS(th)
∆VGS(th)
∆T
J
R
DS(on)
I
D(on)
g
FS
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
t
rr
Q
rr
Notes:
1. R
θJA
R
θJC
Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA30 V
Breakdown Voltage Temperature
ID = 250 µA, Referenced to 25 °C 26 mV/ °C
Coefficient
Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V
VDS = 24 V, VGS = 0 V, TJ= 55 °C
Gate–Source Leakage VGS = ±20 V, VDS = 0 V
(Note 2)
1
µA
10
±100 nA
Gate Threshold Voltage VDS = VGS, ID = 250 µA 1 1.9 3 V
Gate Threshold Voltage
ID = 250 µA, Referenced to 25 °C –4.6 mV/ °C
Temperature Coefficient
Static Drain–Source
On–Resistance
VGS = 10 V, ID = 5.5 A
VGS = 4.5 V, ID = 4.8 A
VGS = 10 V, ID = 5.5 A, TJ= 125 °C
31
40
45
38
50
62
m Ω
On–State Drain Current VGS = 10 V, VDS = 5 V 20 A
Forward Transconductance VDS = 5 V, ID = 5.5 A 19 S
Input Capacitance VDS = 15 V, V
Output Capacitance 90 120 pF
f = 1.0 MHz
GS
= 0 V,
310 412 pF
Reverse Transfer Capacitance 40 60 pF
Gate Resistance VGS = 15 mV, f = 1.0 MHz 1.9
(Note 2)
Turn–On Delay Time VDD = 15 V, ID = 1 A,
Turn–On Rise Time 612 ns
VGS = 10 V, R
GEN
= 6 Ω
612 ns
Ω
Turn–Off Delay Time 16 28 ns
Turn–Off Fall Time 24 ns
Total Gate Charge VDS = 15 V, ID = 5.5 A,
Gate–Source Charge 1.0 nC
VGS = 5 V
2.7 3.8 nC
Gate–Drain Charge 0.7 nC
Maximum Continuous Drain–Source Diode Forward Current 1.3 A
Drain–Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A (Note 2) 0.8 1.2 V
Diode Reverse Recovery Time
(note3)
IF = 5.5 A, diF/dt = 100 A/µs 16 32 nS
Diode Reverse Recovery Charge 6 nC
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
is guaranteed by design while R
a) 78°C/W when mounted
is determined by the user's board design.
θCA
2
on a 0.5 in
copper
pad of 2 oz
b) 125°C/W when
mounted on a 0.02 in
pad of 2 oz copper
2
c) 135°C/W when
mounted on a
minimum pad.
®
MOSFET
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300 µs, Duty Cycle < 2.0%
3. Trr parameter will not be subjected to 100% production testing.
FDS6930B Rev. A1
2 www.fairchildsemi.com
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