Fairchild FDS6892AZ service manual
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FDS6892AZ
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FDS6892AZ
Dual N-Channel Logic Level PWM Optimized PowerTrench MOSFET
October 2001
General Description
These N-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are well suited for low voltage and
battery powered applications where low in-line power
loss and fast switching are required.
D1
D
D1
D
D2
D
D2
D
S2
G1
S1
S
G2
S
S
=25oC unless otherwise noted
A
SO-8
SO-8
Pin 1
Absolute Maximum Ratings T
Features
• 7.5 A, 20 V. R
• Low gate charge (12 nC typical)
• High performance trench technology for extremely
low R
DS(ON)
• High power and current handling capability
= 18 mΩ @ VGS = 4.5 V
DS(ON)
R
= 24 mΩ @ VGS = 2.5 V
DS(ON)
Q1
Q2
45
36
27
18
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
STG
Drain-Source Voltage 20 V
Gate-Source Voltage ± 12 V
Drain Current – Continuous (Note 1a) 7.5 A
– Pulsed 30
Power Dissipation for Dual Operation 2
Power Dissipation for Single Operation (Note 1a) 1.6
(Note 1b)
(Note 1c)
Operating and Storage Junction Temperature Range –55 to +150
1
0.9
W
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient (Note 1a) 78
Thermal Resistance, Junction-to-Case (Note 1) 40
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
FDS6892AZ FDS6892AZ 13’’ 12mm 2500 units
2001 Fairchild Semiconductor Corporation
°C/W
°C/W
FDS6892AZ Rev C (W)
Electrical Characteristics T
FDS6892AZ
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BVDSS
∆T
I
DSS
I
GSSF
I
GSSR
Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 µA 20 V
Breakdown Voltage Temperature
Coefficient
J
ID = 250 µA, Referenced to 25°C
14
Zero Gate Voltage Drain Current VDS = 16 V, VGS = 0 V
VDS = 16 V, VGS = 0 V, TJ = 55°C
Gate–Body Leakage, Forward VGS = 12 V, VDS = 0 V 10
Gate–Body Leakage, Reverse VGS = –12 V, VDS = 0 V –10
mV/°C
1
10
On Characteristics (Note 2)
V
GS(th)
∆VGS(th)
∆T
R
DS(on)
I
D(on)
g
FS
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.6 1.0 1.5 V
Gate Threshold Voltage
Temperature Coefficient
J
Static Drain–Source
On–Resistance
ID = 250 µA, Referenced to 25°C
VGS = 4.5 V, ID = 7.5 A
VGS = 2.5 V, ID = 6.5 A
VGS = 4.5 V,ID = 7.5 A,TJ = 125°C
–3
13
18
19
On–State Drain Current VGS = 4.5V, VDS = 5 V 15 A
Forward Transconductance VDS = 5 V, ID = 7.5 A 36 S
mV/°C
18
24
28
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance 1286 pF
Output Capacitance 305 pF
Reverse Transfer Capacitance
VDS = 10 V, V
f = 1.0 MHz
GS
= 0 V,
161 pF
Switching Characteristics (Note 2)
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
g
gs
gd
Turn–On Delay Time 10 20 ns
Turn–On Rise Time 14 25 ns
VDD = 10 V, ID = 1 A,
VGS = 4.5 V, R
GEN
= 6 Ω
Turn–Off Delay Time 25 40 ns
Turn–Off Fall Time
Total Gate Charge 12 17 nC
Gate–Source Charge 2.6 nC
VDS = 10 V, ID = 7.5 A,
VGS = 4.5 V
Gate–Drain Charge
8 16 ns
3 nC
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
Maximum Continuous Drain–Source Diode Forward Current 1.3 A
Drain–Source Diode Forward
VGS = 0 V, IS = 1.3 A (Note 2) 0.7 1.2 V
Voltage
is guaranteed by design while R
θJC
is determined by the user's board design.
θCA
µA
µA
µA
mΩ
a) 78°C/W when
mounted on a 0.5in
pad of 2 oz copper
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
2
b) 125°C/W when
mounted on a 0.02
in2 pad of 2 oz
copper
c) 135°C/W when mounted on a
minimum mounting pad.
FDS6892AZ Rev C (W)
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