Fairchild FDN361BN service manual
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October 2005
FDN361BN
30V N-Channel, Logic Level, PowerTrench® MOSFET
FDN361BN 30V N-Channel, Lo
General Description
These N-Channel Logic Level MOSFETs are produced
using Fairchild Semiconductor’s advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
superior switching performance.
These devices are particularly suited for low voltage
applications in notebook computers, portable phones,
PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are
needed in a very small outline surface mount package.
D
S
SuperSOT -3
TM
Absolute Maximum Ratings T
G
o
=25
C unless otherwise noted
A
Features
• 1.8 A, 30 V. R
R
• Low gate charge
• Industry standard outline SOT-23 surface mount
package using proprietary SuperSOT
superior thermal and electrical capabilities
• High performance trench technology for extremely
DS(ON)
low R
= 110 mΩ @ VGS = 10 V
DS(ON)
= 160 mΩ @ VGS = 4.5 V
DS(ON)
D
G
S
TM
-3 design for
ic Level, PowerTrench
®
MOSFET
Symbol Parameter Ratings Units
V
Drain-Source Voltage 30 V
DSS
V
Gate-Source Voltage
GSS
ID Drain Current – Continuous (Note 1a) 1.4 A
– Pulsed 10
PD
TJ, T
STG
Power Dissipation for Single Operation (Note 1a) 0.5
Operating and Storage Junction Temperature Range –55 to +150
(Note 1b)
± 20
0.46
V
W
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a) 250
(Note 1) 75
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
361B FDN361BN 7’’ 8mm 3000 units
©2005 Fairchild Semiconductor Corporation
FDN361BN Rev A(W)
www.fairchildsemi.com
°C/W
FDN361BN 30V N-Channel, Logic Level, PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
Drain–Source Breakdown Voltage
DSS
ΔBVDSS
ΔT
I
Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1
DSS
Breakdown Voltage Temperature
Coefficient
J
I
Gate–Body Leakage
GSS
= 0 V, ID = 250 μA
V
GS
I
= 250 μA,Referenced to 25°C
D
= 24 V, VGS = 0 V, TJ = 55°C
V
DS
= ±20 V, VDS = 0 V
V
GS
30 V
26
mV/°C
μA
10
±100
μA
nA
On Characteristics (Note 2)
V
Gate Threshold Voltage
GS(th)
R
Static Drain–Source
DS(on)
On–Resistance
I
On–State Drain Current VGS = 4.5 V, VDS = 5 V 3.5 A
D(on)
V
= VGS, ID = 250 μA
DS
VGS = 10 V, ID = 1.4 A
= 4.5 V, ID = 1.2 A
V
GS
V
= 10 V, ID = 1.4 A, TJ = 125°C
GS
1 2.1 3 V
92
120
114
110
160
150
mΩ
gFS Forward Transconductance VDS = 5 V, ID = 1.4 A 4 S
Dynamic Characteristics
C
Input Capacitance 145 193 pF
iss
C
Output Capacitance 35 47 pF
oss
C
Reverse Transfer Capacitance
rss
RG Gate Resistance
V
= 15 V, V
DS
GS
f = 1.0 MHz
= 15 mV, f = 1.0 MHz
V
GS
= 0 V,
15 23 pF
1.6
Ω
Switching Characteristics (Note 2)
t
Turn–On Delay Time 3 6 ns
d(on)
tr Turn–On Rise Time 8 16 ns
t
Turn–Off Delay Time 16 29 ns
d(off)
tf Turn–Off Fall Time
Qg Total Gate Charge 1.3 1.8 nC
Qgs Gate–Source Charge 0.5 nC
Qgd Gate–Drain Charge
= 15 V, ID = 1 A,
V
DD
= 10 V, R
V
GS
= 15 V, ID = 1.4 A,
V
DS
= 4.5 V
V
GS
GEN
= 6 Ω
2 4 ns
0.5 nC
®
MOSFET
Drain–Source Diode Characteristics
VSD Drain–Source Diode Forward
Voltage
trr
Qrr
Notes:
1. R
θJA
the drain pins. R
Diode Reverse Recovery Time
Diode Reverse Recovery Charge
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
is guaranteed by design while R
θJC
a) 250°C/W when mounted on a
2
pad of 2 oz. copper.
0.02 in
θCA
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2.0%
FDN361BN Rev A(W) www.fairchildsemi.com
VGS = 0 V, IS = 0.42 A (Note 2) 0.8 1.2 V
IF = 1.4 A, diF/dt = 100 A/µs 11 22 nS
4 nC
is determined by the user's board design.
b) 270°C/W when mounted on a
minimum pad.
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