Fairchild FDN352AP service manual
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FDN352AP
Single P-Channel, PowerTrench
®
MOSFET
FDN352AP Single P-Channel, PowerTrench
August 2005
Features
–1.3 A, –30V R
–1.1 A, –30V R
High performance trench technology for extremely low
R
DS(ON)
High power version of industry Standard SOT-23 package.
Identical pin-out to SOT-23 with 30% higher power handling
capability.
= 180 m Ω @ V
DS(ON)
= 300 m Ω @ V
DS(ON)
= –10V
GS
= –4.5V
GS
Applications
Notebook computer power management
D
S
G
G
SuperSOT™-3
General Description
This P-Channel Logic Level MOSFET is produced using Fairchild Semiconductor advanced Power Trench process that has
been especially tailored to minimize the on-state resistance and
yet maintain low gate charge for superior switching performance.
These devices are well suited for low voltage and battery powered applications where low in-line power loss is needed in a
very small outline surface mount package.
D
G S
®
MOSFET
T
Absolute Maximum Ratings
= 25°C unless otherwise noted
A
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
T
, T
J
STG
Thermal Characteristics
R
JA
R
JC
Drain-Source Voltage –30 V
Gate-Source Voltage
Drain Current – Continuous (Note 1a) –1.3 A
– Pulsed –10
Power Dissipation for Single Operation (Note 1a) 0.5 W
(Note 1b) 0.46
Operating and Storage Junction Temperature Range –55 to +150
Thermal Resistance, Junction-to-Ambient (Note 1a) 250
Thermal Resistance, Junction-to-Case (Note 1) 75
25 V
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
52AP FDN352AP 7’’ 8mm 3000 units
©2005 Fairchild Semiconductor Corporation
FDN352AP Rev. C1
1
C/W
www.fairchildsemi.com
θ
θ
θ
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∆
µ
±
∆
T
Electrical Characteristics
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
BV
∆ T
I
DSS
I
GSS
On Characteristics (Note 2)
V
GS(th)
V
GS(th)
∆ T
R
DS(on)
g
FS
Dynamic Characteristics
C
iss
C
oss
C
rss
Switching Characteristics (Note 2)
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Drain–Source Diode Characteristics and Maximum Ratings
I
S
V
SD
t
rr
Q
rr
Notes:
1. R
surface of the drain pins R
(a) R
(b) R
2. Pulse Test: Pulse Width < 300 µ s, Duty Cycle < 2.0%
Drain–Source Breakdown Voltage V
Breakdown Voltage Temperature Coefficient I
DSS
J
Zero Gate Voltage Drain Current V
Gate–Body Leakage V
Gate Threshold Voltage V
Gate Threshold Voltage
Temperature Coefficient
J
Static Drain–Source
On–Resistance
Forward Transconductance V
Input Capacitance V
= 0 V, I
GS
= –250 µ A, Referenced to 25 ° C –17 mV/ ° C
D
= –24 V, V
DS
= ± 25 V, V
GS
= V
DS
I
= –250 µ A, Referenced to 25 ° C4mV/ ° C
D
V
= –10 V, I
GS
V
= –4.5 V, I
GS
V
= –4.5 V, I
GS
= –5 V, I
DS
= –15 V, V
DS
= –250 µ A –30 V
D
= 0 V –1
GS
= 0 V
DS
, I
= –250 µ A –0.8 –2.0 –2.5 V
GS
D
= –1.3 A
D
= –1.1 A
D
= –1.1 A, T
D
= –0.9 A 2.0 S
D
= 0 V, f = 1.0 MHz 150 pF
GS
= 125 ° C
J
150
250
330
100 nA
180
300
400
Output Capacitance 40 pF
Reverse Transfer Capacitance 20 pF
Tu r n–On Delay Time V
Tu r n–On Rise Time 15 28 ns
= –10 V, I
DD
V
= –10 V, R
GS
= –1 A,
D
GEN
48ns
= 6 Ω
Tu r n–Off Delay Time 10 18 ns
Tu r n–Off Fall Time 12ns
Total Gate Charge V
Gate–Source Charge 0.5 nC
DS
V
GS
= –10V, I
= –4.5 V
= –0.9 A,
D
1.4 1.9 nC
Gate–Drain Charge 0.5 nC
Maximum Continuous Drain–Source Diode Forward Current –0.42 A
Drain–Source Diode Forward Voltage V
Diode Reverse Recovery Time I
Diode Reverse Recovery Charge 7 nC
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting
JA
= 250°C/W when mounted on a 0.02 in
JA
= 270°C/W when mounted on a 0.001 in
JA
is guaranteed by design while R
JC
2
pad of 2oz. copper.
2
pad of 2oz. copper.
= 0 V, I
GS
= –3.9 A,
F
dI
/dt = 100 A/µs
F
is determined by the user’s board design.
JA
= –0.42 A (Note 2) –0.8 –1.2 V
S
17 ns
m Ω
FDN352AP Single P-Channel, PowerTrench
A
®
MOSFET
FDN352AP Rev. C1
2
www.fairchildsemi.com
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