Fairchild FDN337N service manual
March 1998
FDN337N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description Features
SuperSOTTM-3 N-Channel logic level enhancement mode
power field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. These devices are particularly suited for
low voltage applications in notebook computers, portable
phones, PCMCIA cards, and other battery powered circuits
where fast switching, and low in-line power loss are needed
in a very small outline surface mount package.
SOT-23
SuperSOTTM-6
SuperSOTTM-8
D
337
S
SuperSOT -3
TM
G
2.2 A, 30 V, R
R
= 0.065 Ω @ VGS = 4.5 V
DS(ON)
= 0.082 Ω @ VGS = 2.5 V.
DS(ON)
Industry standard outline SOT-23 surface mount
package using proprietary SuperSOTTM-3 design for
superior thermal and electrical capabilities.
High density cell design for extremely low R
DS(ON)
Exceptional on-resistance and maximum DC current
capability.
SO-8
SOT-223
D
G
SOIC-16
S
.
Absolute Maximum Ratings T
= 25oC unless other wise noted
A
Symbol Parameter FDN337N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 30 V
Gate-Source Voltage - Continuous ±8 V
Drain/Output Current - Continuous 2.2 A
- Pulsed 10
P
D
TJ,T
Maximum Power Dissipation (Note 1a) 0.5 W
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
STG
0.46
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
Thermal Resistance, Junction-to-Ambient (Note 1a) 250 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 75 °C/W
© 1998 Fairchild Semiconductor Corporation
FDN337N Rev.C
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
I
GSSF
I
GSSR
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
ID = 250 µA, Referenced to 25 oC
VDS = 24 V, V
GS
= 0 V
41
1 µA
TJ = 55°C
Gate - Body Leakage, Forward VGS = 8 V,VDS = 0 V 100 nA
Gate - Body Leakage, Reverse
VGS = -8 V, VDS = 0 V
mV/ oC
10 µA
-100 nA
ON CHARACTERISTICS (Note)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.4 0.7 1 V
Gate Threshold Voltage Temp. Coefficient
/∆T
J
Static Drain-Source On-Resistance
ID = 250 µA, Referenced to 25 oC
VGS = 4.5 V, ID = 2.2 A
-2.3
0.054 0.065
mV/ oC
TJ =125°C 0.08 0.11
0.07 0.082
13 S
I
g
D(ON)
FS
VGS = 2.5 V, ID = 2 A
On-State Drain Current VGS = 4.5 V, VDS = 5 V 10 A
Forward Transconductance
VDS = 5 V, ID = 2.2 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 10 V, VGS = 0 V,
Output Capacitance 145 pF
f = 1.0 MHz
300 pF
Reverse Transfer Capacitance 35 pF
SWITCHING CHARACTERISTICS (Note)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 10 18 ns
VDD = 5 V, ID = 1 A,
VGS = 4.5 V, R
GEN
= 6 Ω
Turn - Off Delay Time 17 28 ns
Turn - Off Fall Time 4 10 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 1.1 nC
Gate-Drain Charge 1.9 nC
VDS = 10 V, ID = 2.2 A,
VGS = 4.5 V
4 10 ns
7 9 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Note:
1. R
JA
θ
design while R
Typical R
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Maximum Continuous Drain-Source Diode Forward Current 0.42 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.42 A (Note) 0.65 1.2 V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design.
CA
θ
using the board layouts shown below on FR-4 PCB in a still air environment :
JA
θ
is guaranteed by
JC
θ
Ω
a. 250
0.02 in2 pad of 2oz Cu.
o
C/W when mounted on a
o
b. 270
C/W when mounted on
2
a 0.001 in
pad of 2oz Cu.
FDN337N Rev.C
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