Fairchild FDMS9620S service manual
tm
FDMS9620S
Power 56
4
3
2
1
5
6
7
8
S2
S2
S2
G2
D1
D1
D1
G1
G1
D1
D1
D1
S1/D2
G2
S2
S2
S2
D1
G1
D1
D1
D1
S1/D2
G2
S2
S2
S2
D1
Dual N-Channel PowerTrench® MOSFET
Q1: 30V, 16A, 21.5mΩ Q2: 30V, 18A, 13mΩ
Features
Q1: N-Channel
Max r
Max r
Q2: N-Channel
Max r
Max r
Low Qg high side MOSFET
Low r
Thermally efficient dual Power 56 package
Pinout optimized for simple PCB design
RoHS Compliant
= 21.5mΩ at VGS = 10V, ID = 7.5A
DS(on)
= 29.5mΩ at VGS = 4.5V, ID = 6.5A
DS(on)
= 13mΩ at VGS = 10V, ID = 10A
DS(on)
= 17mΩ at VGS = 4.5V, ID = 8.5A
DS(on)
low side MOSFET
DS(on)
General Description
This device includes two specialized MOSFETs in a unique dual
Power 56 package. It is designed to provide an optimal
Synchronous Buck power stage in terms of efficiency and PCB
utilization. The low switching loss "High Side" MOSFET is
complemented by a Low Conduction Loss "Low Side" SyncFET .
Applications
Synchronous Buck Converter for:
Notebook System Power
General Purpose Point of Load
FDMS9620S Dual N-Channel PowerTrench
July 2007
®
MOSFET
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
P
D
, T
T
J
STG
Thermal Characteristics
R
θJC
θJA
R
θJA
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
©2007 Fairchild Semiconductor Corporation
FDMS9620S Rev.D2
FDMS9620S FDMS9620S Power 56 13” 12mm 3000 units
Drain to Source Voltage 30 30 V
Gate to Source Voltage ±20 ±20 V
Drain Current -Continuous (Package limited) TC = 25°C 16 18
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 60 60
Power Dissipation for Single Operation TA = 25°C (Note 1a) 2.5
T
Operating and Storage Junction Temperature Range -55 to +150 °C
Thermal Resistance, Junction to Case 8.2 3.1
Thermal Resistance, Junction to Ambient (Note 1a) 50
Thermal Resistance, Junction to Ambient (Note 1b) 120
= 25°C unless otherwise noted
A
= 25°C 21 44
C
= 25°C (Note 1a) 7.5 10
A
= 25°C (Note 1b) 1
A
1
A
W
°C/WR
www.fairchildsemi.com
FDMS9620S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
ΔBV
ΔT
I
DSS
I
GSS
DSS
DSS
J
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current VDS = 24V, V
ID = 250μA, VGS = 0V
ID = 1mA, VGS = 0V
ID = 250μA, referenced to 25°C
ID = 1mA, referenced to 25°C
= 0V
GS
Gate to Source Leakage Current VGS = ±20V, VDS= 0V
Q1Q230
30
Q1
Q2
Q1
Q2
Q1
Q2
V
23
23
mV/°C
1
500
±100
±100
On Characteristics
V
GS(th)
ΔV
ΔT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Drain to Source On Resistance
Forward Transconductance
VGS = VDS, ID = 250μA
VGS = VDS, ID = 1mA
ID = 250μA, referenced to 25°C
ID = 1mA, referenced to 25°C
VGS = 10V, ID = 7.5A
VGS = 4.5V, ID = 6.5A
VGS = 10V , ID = 7.5A , TJ = 125°C
VGS = 10V, ID = 10A
VGS = 4.5V, ID = 8.5A
VGS = 10V, ID = 10A , TJ = 125°C
VDD = 10V, ID = 7.5A
VDD = 10V, ID = 10A
Q1Q21
Q1
Q2
Q1
Q2
Q1
Q2
1.6
1
1.6
-4
-4
18
23
25
9
13
14
3
3
mV/°C
21.5
29.5
32
13
17
22
25
27
μA
nA
V
mΩ
S
®
MOSFET
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance f = 1MHz
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
= 15V, VGS = 0V, f = 1MHZ
DS
VDD = 15V, ID = 1A,
V
= 10V, R
GS
GEN
= 6Ω
Q1
VDD = 15V, V
= 10V ,ID = 7.5A
GS
Q2
VDD = 15V, V
= 10V ,ID = 10A
GS
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
500
700
100
500
100
0.9
1.8
2.3
1.7
2.8
2.0
3.6
65
11
15
13
23
27
10
18
665
935
135
665
100
150
pF
pF
pF
Ω
20
27
7
14
24
37
44
10
7
14
14
25
ns
ns
ns
ns
nC
nC
nC
©2007 Fairchild Semiconductor Corporation
FDMS9620S Rev.D2
2
www.fairchildsemi.com
FDMS9620S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
I
S
V
SD
t
rr
Q
rr
Notes:
1: R
is determined with the device mount ed on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJA
the user's board design.
Maximum Continuous Drain-Source Diode Forward Current
V
= 0V, IS = 2.1A (Note 2)
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
a.50°C/W when mounted on
a 1 in2 pad of 2 oz copper
GS
V
= 0V, IS = 3.5A (Note 2)Q1Q2
GS
Q1
I
= 7.5A, di/dt = 100A/μs
F
Q2
I
= 10A, di/dt = 300A/μs
F
Q1
Q2
0.7
0.5
Q1
Q2
Q1
Q2
is guaranteed by design while R
θJC
b. 120°C/W when mounted on a
minimum pad of 2 oz copper
13
14
2.1
3.5
1.2
1.0
4
9
is determined by
θCA
A
V
ns
nC
®
MOSFET
2: Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%.
©2007 Fairchild Semiconductor Corporation
FDMS9620S Rev.D2
3
www.fairchildsemi.com
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