Fairchild FDMS9600S service manual
tm
FDMS9600S
Dual N-Channel PowerTrench® MOSFET
Q1: 30V, 32A, 8.5mΩ Q2: 30V, 30A, 5.5mΩ
Features
Q1: N-Channel
Max r
Max r
Q2: N-Channel
Max r
Max r
Low Qg high side MOSFET
Low r
Thermally efficient dual Power 56 package
Pinout optimized for simple PCB design
RoHS Compliant
= 8.5mΩ at VGS = 10V, ID = 12A
DS(on)
= 12.4mΩ at VGS = 4.5V, ID = 10A
DS(on)
= 5.5mΩ at VGS = 10V, ID = 16A
DS(on)
= 7.0mΩ at VGS = 4.5V, ID = 14A
DS(on)
low side MOSFET
DS(on)
General Description
This device includes two specialized MOSFETs in a unique dual
Power 56 package. It is designed to provide an optimal
Synchronous Buck power stage in terms of efficiency and PCB
utilization. The low switching loss "High Side" MOSFET is com-
plemented by a Low Conduction Loss "Low Side" SyncFET.
Applications
Synchronous Buck Converter for:
Notebook System Power
General Purpose Point of Load
FDMS9600S Dual N-Channel PowerTrench
September 2008
®
MOSFET
G1
G2
G2
S2
S2
S2
S2
S2
S2
Power 56
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
P
D
, T
T
J
STG
Drain to Source Voltage 30 30 V
Gate to Source Voltage ±20 ±20 V
Drain Current -Continuous (Package limited) TC = 25°C 32 30
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 60 60
Power Dissipation for Single Operation (Note 1a) 2.5
(Note 1b) 1.0
Operating and Storage Junction Temperature Range -55 to +150 °C
G1
D1
D1
D1
D1
D1
D1
S1/D2
S1/D2
= 25°C unless otherwise noted
A
D1
D1
= 25°C 55 108
C
= 25°C (Note 1a) 12 16
A
Q2
5
6
7
8
4
3
2
1
Q 1
Thermal Characteristics
R
θJA
θJA
R
θJC
Thermal Resistance, Junction to Ambient (Note 1a) 50
Thermal Resistance, Junction to Ambient (Note 1b) 120
Thermal Resistance, Junction to Case 3 1.2
Package Marking and Ordering Information
A
W
°C/WR
Device Marking Device Package Reel Size Tape Width Quantity
FDMS9600S FDMS9600S Power 56 13” 12mm 3000 units
©2008 Fairchild Semiconductor Corporation
FDMS96
00S Rev.D
1
1
www.fairchi
ldsemi.com
FDMS9600S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Typ e Min Typ Max Units
Off Characteristics
BV
∆BV
∆T
I
DSS
I
GSS
DSS
DSS
J
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current VDS = 24V, V
Gate to Source Leakage Current VGS = ±20V, VDS= 0V
On Characteristics
V
GS(th)
∆V
∆T
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Drain to Source On Resistance
Forward Transconductance
= 250µA, VGS = 0V
I
D
= 1mA, VGS = 0V
I
D
ID = 250µA, referenced to 25°C
I
= 1mA, referenced to 25°C
D
= 0V
GS
V
= VDS, ID = 250µA
GS
= VDS, ID = 1mA
V
GS
ID = 250µA, referenced to 25°C
= 1mA, referenced to 25°C
I
D
V
= 10V, ID = 12A
GS
V
= 4.5V, ID = 10A
GS
= 10V, ID = 12A , TJ = 125°C
V
GS
= 10V, ID = 16A
V
GS
= 4.5V, ID = 14A
V
GS
= 10V, ID = 16A , TJ = 125°C
V
GS
= 10V, ID = 12A
V
DD
V
= 10V, ID = 16A
DD
Q1Q230
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
30
1
1
V
35
29
mV/°C
1
500
±100
±100nAnA
1.5
1.8
-4.5
-6.0
7.0
9.2
8.6
4.5
5.3
5.4
3
3
mV/°
8.5
12.4
13.0
5.5
7.0
8.3
54
68
µA
V
mΩ
S
C
®
MOSFET
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance f = 1MHz
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g(TOT)
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
= 15V, VGS = 0V, f= 1MHz
DS
= 10V, ID = 1A,
V
DD
V
GS
= 10V, R
GEN
= 6Ω
Q1
V
DD
= 15V, V
= 4.5V, ID = 12A
GS
Q2
V
DD
= 15V, V
= 4.5V, ID = 16A
GS
Q1
Q2
Q1
Q2
1280
2300
525
1545
Q1
Q2 80250
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1.0
1.7
13
17
11
42
54
12
32
Q1
Q2
Q1
Q2
Q1
Q2
21
2.7
6.5
1705
3060
700
2055
120
375
pF
pF
pF
Ω
23
31
6
12
20
67
86
22
51
9
13
29
3
8
ns
ns
ns
ns
nC
nC
nC
FDMS9600S Rev.D1
2
www.fairchildsemi.com
FDMS9600S Dual N-Channel PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
I
S
V
SD
t
rr
Q
rr
Notes:
1: R
θJA
the user's board design.
Maximum Continuous Drain-Source Diode Forward Current
= 0V, IS = 2.1A (Note 2)
V
GS
V
= 0V, IS = 3.5A
Source to Drain Diode
Forward Voltage
VGS = 0V, IS = 8.2A (Note 2) Q2 0.5 1.0
Reverse Recovery Time
Reverse Recovery Charge
is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
a.50°C/W when mounted on
a 1 in2 pad of 2 oz copper
GS
Q1
= 12A, di/dt = 100A/µs
I
F
Q2
= 16A, di/dt = 300A/µs
I
F
(Note 2)
Q1
Q2
Q1
Q2
0.7
0.4
Q1
Q2
Q1
Q2
is guaranteed by design while R
θJC
b. 120°C/W when mounted on a
minimum pad of 2 oz copper
33
27
20
33
2.1
3.5
1.2
1.0
is determined by
θCA
A
V
ns
nC
®
MOSFET
2: Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.
FDMS9600S Rev.D1
3
www.fairchildsemi.com
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