Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
= 8 mΩ at VGS = 10 V, ID = 13 A
DS(on)
= 11 mΩ at VGS = 4.5 V, ID = 11 A
DS(on)
= 2.8 mΩ at VGS = 10 V, ID = 23 A
DS(on)
= 3.8 mΩ at VGS = 4.5 V, ID = 21 A
DS(on)
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
Notebook VCORE
Drain to Source Voltage3030V
Gate to Source Voltage (Note 3)±20±20V
Drain Current -Continuous (Package limited) TC = 25 °C3055
-Continuous (Silicon limited) T
-Continuous T
-Pulsed40100
Single Pulse Avalanche Energy 40
Power Dissipation for Single Operation TA = 25 °C2.2
Power Dissipation for Single Operation T
Operating and Storage Junction Temperature Range-55 to +150°C
Thermal Resistance, Junction to Ambient 57
Thermal Resistance, Junction to Ambient 125
Thermal Resistance, Junction to Case 3.52.0
22CA
F10CC
FDMS3686SPower 5613 ”12 mm3000 units
= 25 °C unless otherwise noted
A
1
= 25 °C54123
C
= 25 °C13
A
= 25 °C1.0
A
1a
4
1a
1c
1a
1c
1b
23
4
60
1b
2.5
1d
1.0
1b
50
1d
120
www.fairchildsemi.com
A
mJ
W
°C/WR
FDMS3686S PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
SymbolParameterTest ConditionsTypeMinTypMaxUnits
Off Characteristics
BV
ΔBV
ΔT
I
DSS
I
GSS
DSS
DSS
J
= 250 μA, VGS = 0 V
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
D
I
= 1 mA, VGS = 0 V
D
ID = 250 μA, referenced to 25 °C
I
= 10 mA, referenced to 25 °C
D
Zero Gate Voltage Drain CurrentVDS = 24 V, V
Gate to Source Leakage Current,
Forwad
V
= 20 V, VDS= 0 V
GS
GS
= 0 V
Q1Q230
30
Q1
Q2
Q1
Q2
Q1
Q2
V
15
19
500
100
100
mV/°C
1
I
On Characteristics
V
V
GS(th)
ΔV
ΔT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
4. Q1: EAS of 40 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14 A.
of 60 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 11 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 17 A.
Q2: E
AS
G
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper