FDMS3624S
Power 56
G1
D1
D1
D1
G2
S2
S2
S2
D1
PHASE
(S1/D2)
Top Bottom
Pin 1
Pin 1
PowerTrench® Power Stage
25V Asymmetric Dual N-Channel MOSFET
FDMS3624S PowerTrench
December 2011
Features
Q1: N-Channel
Max r
Max r
Q2: N-Channel
Max r
Max r
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
= 5.0 mΩ at V GS = 10 V, ID = 17.5 A
DS(on)
= 5.7 mΩ at V GS = 4.5 V, ID = 16 A
DS(on)
= 1.8 mΩ at V GS = 10 V, ID = 30 A
DS(on)
= 2.2 mΩ at V GS = 4.5 V, ID = 27 A
DS(on)
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
Notebook VCORE
®
Power Stage
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
E
AS
P
D
TJ, T
STG
Drain to Source Voltage 25 25 V
Gate to Source Voltage (Note 4) ±12 ±12 V
Drain Current -Continuous (Package limited) TC = 25 °C 30 60
-Pulsed 70 120
Single Pulse Avalanche Energy (Note 3) 29 86 mJ
Power Dissipation for Single Operation TA = 25 °C 2.2
Power Dissipation for Single Operation T
Operating and Storage Junction Temperature Range -55 to +150 °C
= 25 °C unless otherwise noted
A
= 25 °C 17.5
A
= 25 °C 1.0
A
1a
1a
1c
30
2.5
1.0
1b
1b
1d
A -Continuous T
W
Thermal Characteristics
R
θJA
θJA
R
θ JC
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
©2011 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FDMS3624S Rev.C2
Thermal Resistance, Junction to Ambient 57
Thermal Resistance, Junction to Ambient 125
Thermal Resistance, Junction to Case 3.0 2.2
08OD
07OD
FDMS3624S Power 56 13 ” 12 mm 3000 units
1a
1c
50
120
1b
1d
°C/W R
FDMS3624S PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
ΔBV
ΔT
I
DSS
I
GSS
DSS
DSS
J
= 250 μ A, VGS = 0 V
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current VDS = 20 V, V
D
I
= 1 mA, VGS = 0 V
D
ID = 250 μ A, referenced to 25 °C
I
= 10 mA, referenced to 25 °C
D
= 0 V
GS
Gate to Source Leakage Current VGS = 12 V/-8 V, VDS= 0 V
Q1Q225
25
Q1
Q2
Q1
Q2
Q1
Q2
V
12
24
500
±100
±100nAnA
mV/°C
1
I
On Characteristics
V
V
GS(th)
ΔV
ΔT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Drain to Source On Resistance
Forward Transconductance
= VDS, ID = 250 μA
GS
V
= VDS, ID = 1 mA
GS
ID = 250 μ A, referenced to 25 °C
I
= 10 mA, referenced to 25 °C
D
= 10 V, ID = 17.5 A
V
GS
V
= 4.5 V, ID = 16 A
GS
V
= 10 V , ID = 17.5 A,TJ =125 °C
GS
V
= 10 V, ID = 30 A
GS
V
= 4.5 V, ID = 27 A
GS
V
= 10 V, ID =30 A ,TJ =125 °C
GS
V
= 5 V, ID = 17.5 A
DS
V
= 5 V, ID = 30 A
DS
Q1Q20.8
1.1
Q1
Q2
Q1
Q2
Q1
Q2
1.2
1.4
-4
-3
3.8
4.4
5.4
1.5
1.8
2.1
100
240
2.0
2.2
mV/°C
5.0
5.7
7.0
1.8
2.2
2.7
μA
μA
V
mΩ
S
®
Power Stage
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
Q
g
g
gs
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge V
Total Gate Charge V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Q1:
= 13 V, VGS = 0 V, f = 1 MHZ
V
DS
Q2:
= 13 V, VGS = 0 V, f = 1 MHZ
V
DS
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
1570
4045
448
946
61
117
0.4
0.9
pF
pF
pF
Ω
7
11
2
5
23
39
2
4
26
59
12
27
3.3
8.2
2.7
7.6
ns
ns
ns
ns
nC
nC
nC
nC
Q1:
= 13 V , ID = 17.5 A, R
V
DD
Q2:
= 13 V, ID = 30A, R
V
DD
= 0 V to 10 V
GS
= 0 V to 4.5 V
GS
= 6 Ω
GEN
= 6 Ω
GEN
Q1
V
= 13 V,
DD
I
= 17.5 A
D
Q2
VDD = 13 V,
I
= 30 A
D
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
©2011 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com
FDMS3624S Rev.C2
FDMS3624S PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
0.8
0.8
23
28
28
1.2
1.2
9
is determined by
θ CA
V
= 0 V, IS = 17.5 A (Note 2)
V
SD
t
rr
Q
rr
Notes:
1.R
is determined with the device mo un ted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. boar d o f FR - 4 mat er i al. R
θ JA
the user's board design.
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
a. 57 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SF
SS
DS
DF
G
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
GS
V
= 0 V, IS = 30 A (Note 2)Q1Q2
GS
Q1
= 17.5 A, di/dt = 100 A/μs
I
F
Q2
I
= 30 A, di/dt = 300 A/μs
F
G
DF
DS
Q1
Q2
Q1
Q2
is guaranteed by design while R
θ JC
b. 50 °C/W when mounted on
a 1 in
SS
SF
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
2
pad of 2 oz copper
ns
nC
V
®
Power Stage
SF
SS
DS
DF
G
2 Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
of 29 mJ is based on starting TJ = 25 oC; N-ch: L = 1.2 mH, IAS = 7 A, VDD = 23 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 16 A.
3. Q1 :E
AS
Q2: EAS of 86 mJ is based on starting TJ = 25 oC; N-ch: L = 0.6 mH, IAS = 17 A, VDD = 23 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 31 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
G
SS
SF
DS
DF
©2011 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com
FDMS3624S Rev.C2
FDMS3624S PowerTrench
0.0 0 .3 0.6 0.9 1.2 1.5
0
10
20
30
40
50
60
70
V
GS
= 2.5 V
V
GS
= 3 V
V
GS
= 10 V
V
GS
= 4.5 V
V
GS
= 3.5 V
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0 1 02 03 04 05 06 07 0
0.5
1.0
1.5
2.0
2.5
3.0
VGS = 2.5 V
VGS = 4.5 V
VGS = 3 V
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
I
D
, DRAIN CURRENT (A)
VGS = 3.5 V
V
GS
= 10 V
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
1.8
ID = 17.5 A
V
GS
= 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANC E
T
J
, JUNCTION TEMPERATURE (
o
C)
234567891 0
0
4
8
12
16
20
TJ = 125 oC
ID = 17.5 A
TJ = 25 oC
V
GS
, GATE TO SOURCE VOLTA G E (V)
r
DS(on)
,
DRAIN TO
SOURCE ON-RESISTANCE
(mΩ )
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
0.5 1.0 1.5 2.0 2.5 3.0
0
10
20
30
40
50
60
70
TJ = 150 oC
V
DS
= 5 V
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
I
D
, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
70
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
V
GS
= 0 V
I
S
, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Typical Characteristics (Q1 N-Channel) T
Figure 1.
On Region Characteristics Figure 2.
= 25°C unless otherwise noted
J
Norma l i z ed On-Res i s t ance
vs Drain Current and Gate Voltage
®
Power Stage
Fig ure 3 . Norm aliz ed On Resis tanc e
vs Junction Temperature
©2011 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com
FDMS3624S Rev.C2
Figure 5. Transfer Characteristics
Figure 4.
On-Resistanc e v s Gate to
Source Voltage
Figure 6.
Source to Dr ain Diode
Forward Voltage vs Source Current