FDMS3615S
G1
D1
D1
D1
G2
S2
S2
S2
D1
PHASE
(S1/D2)
S2
S2
S2
G2
D1
D1
D1
G1
PHASE
Power 56
Top Bottom
Pin 1
PowerTrench® Power Stage
25V Asymmetric Dual N-Channel MOSFET
FDMS3615S PowerTrench
August 2011
Features
Q1: N-Channel
Max r
Max r
Q2: N-Channel
Max r
Max r
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
RoHS Compliant
= 5.8 mΩ at V GS = 10 V, ID = 16 A
DS(on)
= 8.3 mΩ at V GS = 4.5 V, ID = 13 A
DS(on)
= 3.4 mΩ at V GS = 10 V, ID = 18 A
DS(on)
= 4.6 mΩ at V GS = 4.5 V, ID = 15 A
DS(on)
General Description
This device includes two specialized N-Channel MOSFETs in a
dual PQFN package. The switch node has been internally
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
SyncFET (Q2) have been designed to provide optimal power
efficiency.
Applications
Computing
Communications
General Purpose Point of Load
Notebook VCORE
Server
2
5
6
7
8
4
3
2
1
1
®
Power Stage
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
E
AS
P
D
TJ, T
STG
Drain to Source Voltage 25 25 V
Gate to Source Voltage (Note 3) ±20 ±20 V
Drain Current -Continuous (Package limited) TC = 25 °C 23 18
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 45 36
Single Pulse Avalanche Energy 38
Power Dissipation for Single Operation TA = 25°C 2.3
Power Dissipation for Single Operation T
Operating and Storage Junction Temperature Range -55 to +150 °C
= 25°C unless otherwise noted
A
= 25 °C 89 88
C
= 25 °C 16
A
= 25°C 1.0
A
1a
4
1a
1c
18
98
2.3
1.0
1b
5
1b
1d
A
mJ
W
Thermal Characteristics
R
θ JA
R
θ JA
Thermal Resistance, Junction to Ambient 55
Thermal Resistance, Junction to Ambient 125
1a
1c
55
125
1b
°C/W
1d
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
Y8OA
©2011 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com
FDMS3615S Rev.C6
K10OC
FDMS3615S Power 56 13 ” 12
mm 3000 units
FDMS3615S PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
ΔBV
ΔT
I
DSS
I
GSS
DSS
DSS
J
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current V
Gate to Source Leakage Current V
= 250 μ A, VGS = 0 V
D
I
= 1 mA, VGS = 0 V
D
I
= 250 μA, referenced to 25°C
D
I
= 10 mA, referenced to 25°C
D
= 20 V, V
DS
= 20 V, V
GS
GS
DS
= 0 V
= 0 V
Q1Q225
25
Q1
Q2
Q1
Q2
Q1
Q2
V
18
16
mV/°C
1
500
100
100nAnA
I
On Characteristics
V
V
GS(th)
ΔV
ΔT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance
= VDS, I
GS
V
= VDS, I
GS
I
= 250 μA, referenced to 25°C
D
I
= 10 mA, referenced to 25°C
D
= 10 V, ID = 16 A
V
GS
V
= 4.5 V, ID = 13 A
GS
V
= 10 V, ID = 16 A, T
GS
V
= 10 V, ID = 18 A
GS
V
= 4.5 V, ID = 15 A
GS
V
= 10 V, ID = 18 A, T
GS
V
= 5 V, ID = 16 A
DD
V
= 5 V, ID = 18 A
DD
= 250 μA
D
= 1 mA
D
= 125°C
J
= 125°C
J
Q1Q21.2
1.2
Q1
Q2
Q1
Q2
Q1
Q2
1.7
1.8
-5
-6
4.8
6.9
6.6
2.5
3.6
3.4
63
84
2.5
2.5
mV/°C
5.8
8.3
7.9
3.4
4.6
4.1
μ A
V
mΩ
S
®
Power Stage
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g(TOT)
Q
g(TOT)
Q
gs
Q
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge V
Total Gate Charge V
Gate to Source Charge
Gate to Drain “Miller” Charge
1326
Q1:
= 13 V, VGS = 0 V, f = 1 MHZ
V
DS
Q2:
= 13 V, VGS = 0 V, f = 1 MHZ
V
DS
Q1
Q2
Q1
Q2
Q1
Q2
Q1Q20.2
0.2
2175
342
574
78
118
0.9
1.0
1765
2895
455
765
115
180
2.9
3.2
pF
pF
pF
Ω
Q1
V
= 13 V, ID = 16 A, R
DD
Q2
V
= 13 V, ID = 18 A, R
DD
= 0V to 10 V
GS
= 0V to 4.5 V
GS
Q1
V
DD
I
= 16 A
D
Q2
V
DD
I
= 18 A
D
= 6 Ω
GEN
= 6 Ω
GEN
= 13 V,
= 13 V,
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
7.7
9.51519
1.7310
10
19
34
24
49
1.4
2.21010
19
27
31
43
9
13
14
20
3.6
5.7
2.4
3.7
ns
ns
ns
ns
nC
nC
nC
nC
©2011 Fairchild Semiconductor Corporation 2 www.fairchildsemi.com
FDMS3615S Rev.C6
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
0.8
0.8
19
24
19
1.2
1.2
34
38
6
12
35
is determined
θCA
V
= 0 V, IS = 16 A (Note 2)
V
SD
t
rr
Q
rr
Notes:
1. R
is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJA
by the user's board design.
Source-Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
GS
V
= 0 V, IS = 18 A (Note 2)
GS
Q1
I
= 16 A, di/dt = 100 A/s
F
Q2
I
= 18 A, di/dt = 300 A/s
F
Q1
Q2
Q1
Q2
Q1
Q2
is guaranteed by design while R
θJC
ns
nC
FDMS3615S PowerTrench
V
®
Power Stage
a. 55 °C/W when mounted on
2
pad of 2 oz copper
a 1 in
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μ s, Duty cycle < 2.0%.
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
4. EAS of 38 mJ is based on starting TJ = 25 oC; N-ch: L = 0.3 mH, IAS = 16 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14.6 A.
5. EAS of 98 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 14 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 21 A.
b. 55 °C/W when mounted on
2
a 1 in
pad of 2 oz copper
d. 125 °C/W when mounted on a
minimum pad of 2 oz copper
©2011 Fairchild Semiconductor Corporation 3 www.fairchildsemi.com
FDMS3615S Rev.C6
FDMS3615S PowerTrench
0.0 0.5 1.0 1.5
0
9
18
27
36
45
V
GS
= 6 V
V
GS
= 4 V
V
GS
= 10 V
V
GS
= 3 V
V
GS
= 3.5 V
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
I
D
, DRAIN CURRENT (A)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
0 9 18 27 36 45
0
2
4
6
8
VGS = 6 V
VGS = 3.5 V
PULSE DURA TION = 80 μ s
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTA NCE
I
D
, DRAIN CURRENT (A)
V
GS
= 4 V
VGS = 3 V
V
GS
= 10 V
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
ID = 16 A
V
GS
= 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANC E
T
J
, JUNCTION TEMPERATURE (
o
C)
2468
0
5
10
15
20
25
30
TJ = 125 oC
ID = 16 A
TJ = 25 oC
V
GS
, GATE TO SOURCE VOLTAGE (V)
r
DS(on)
,
DRAIN TO
SOURCE ON-RESISTANCE
(mΩ )
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
1234
0
9
18
27
36
45
TJ = 150 oC
V
DS
= 5 V
PULSE DURATION = 80 μ s
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
I
D
, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
0.0 0.2 0.4 0.6 0.8 1.0 1.2
0.001
0.01
0.1
1
10
50
TJ = -55 oC
TJ = 25 oC
TJ = 150 oC
V
GS
= 0 V
I
S
, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Typical Characteristics (Q1 N-Channel) T
Figure 1.
On Region Characteristics Figure 2.
= 25°C unless otherwise noted
J
Normali z e d O n - R esistance
vs Drain Current and Gate Voltage
®
Power Stage
Fig u re 3. Norma l ized O n Res i stanc e
vs Junction Temperature
©2011 Fairchild Semiconductor Corporation 4 www.fairchildsemi.com
FDMS3615S Rev.C6
Figure 5. Transfer Characteristics
Figure 4.
On-Resistance vs Gate to
Source Voltage
Figure 6.
Source to Drain Diode
Forward Voltage vs Source Current
FDMS3615S PowerTrench
0 5 10 15 20
0
2
4
6
8
10
ID = 16 A
V
DD
= 16 V
V
DD
= 10 V
V
GS
, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 13 V
0.1 1 10
50
100
1000
3000
f = 1 MHz
V
GS
= 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
C
rss
C
oss
C
iss
25
0.001 0.01 0.1 1 10 100
1
10
20
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN AVALANCHE (ms)
I
AS
, AVALANCHE CURRENT (A)
25 50 75 100 125 150
0
5
10
15
20
R
θJA
= 55 oC/W
V
GS
= 4.5 V
Limited by Package
V
GS
= 10 V
I
D
, DRAIN CURRENT (A)
T
A
, AMBIENT TEMPERATURE (
o
C)
0.01 0.1 1 10 100200
0.01
0.1
1
10
100
100 μ s
DC
100 ms
10 ms
1 ms
1s
I
D
, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY r
DS(on)
SINGLE PULSE
T
J
= MAX RATED
R
θJA
= 125
o
C/W
T
A
= 25
o
C
10s
10-410-310-210
-1
11 0
100 1000
0.5
1
10
100
1000
SINGLE PULSE
R
θJA
= 125 oC/W
P(
PK
), PEAK TRANSIENT POWER (W)
t, PULSE WIDTH (sec)
Typical Characteristics (Q1 N-Channel) T
Figure 7.
Gate Charge Characteristics Figure 8.
= 25°C unless otherwise noted
J
Capacitance vs Drain
to Source Voltage
®
Power Stage
Figure 9.
Unc l a m p e d I ndu c t i v e
Switching Capability
©2011 Fairchild Semiconductor Corporation 5 www.fairchildsemi.com
FDMS3615S Rev.C6
Figure 11. Forward Bias Safe
Op
erating Area
Figure 10.
Ma ximum Continuous D rai n
Current vs Ambient Temperature
Figure 12.
Si ngle Puls e Maximum
Power Dissipation