Fairchild FDMF6708N service manual

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

April 2012

Benefits

 Ultra-Compact 6x6mm PQFN, 72% Space-Saving

Compared to Conventional Discrete Solutions

 Fully Optimized System Efficiency  Clean Switching Waveforms with Minimal Ringing  High-Current Handling

Features

 Over 93% Peak-Efficiency  High-Current Handling: 50A  High-Performance PQFN Copper-Clip Package  3-State 5V PWM Input Driver  Automatic Diode Emulation (Skip Mode) enabled

through ZCD_EN# Input

 Thermal Warning Flag for Over-Temperature

Condition

 Driver Output Disable Function (DISB# Pin)  Internal Pull-Up and Pull-Down for ZCD_EN# and

DISB# Inputs, Respectively

 Fairchild PowerTrench

Clean Voltage Waveforms and Reduced Ringing

®

Technology MOSFETs for

 Fairchild SyncFET™ (Integrated Schottky Diode)

Technology in Low-Side MOSFET

 Integrated Bootstrap Schottky Diode  Adaptive Gate Drive Timing for Shoot-Through

Protection

 Under-Voltage Lockout (UVLO)  Optimized for Switching Frequencies up to 1MHz  Low-Profile SMD Package  Fairchild Green Packaging and RoHS Compliance  Based on the Intel

®

4.0 DrMOS Standard

Description

The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solution for high-current, highfrequency, synchronous buck DC-DC applications. The FDMF6708N integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6mm package.

With an integrated approach, the complete switching power stage is optimized with regard to driver and MOSFET dynamic performance, system inductance, and power MOSFET R Fairchild's high-performance PowerTrench technology, which dramatically reduces switch ringing, eliminating the need for snubber circuit in most buck converter applications.

A driver IC with reduced dead times and propagation delays further enhances the performance. A thermal warning function warns of a potential over-temperature situation. The FDMF6708N also incorporates a ZeroCross Detect (ZCD_EN#) for improved light-load efficiency. The FDMF6708N also provides a 3-state 5V PWM input for compatibility with a wide range of PWM controllers.

. XS™ DrMOS uses

DS(ON)

®

MOSFET

Applications

Notebook Computers

  High-Performance Gaming Motherboards  Compact Blade Servers & Workstations, V-Core

and Non-V-Core DC-DC Converters

 Desktop Computers, V-Core and Non-V-Core

DC-DC Converters

 High-Current DC-DC Point-of-Load Converters  Networking and Telecom Microprocessor Voltage

Regulators

 Small Form-Factor Voltage Regulator Modules

Ordering Information

Part Number Current Rating Package Top Mark

FDMF6708N 50A 40-Lead, Clipbond PQFN DrMOS, 6.0mm x 6.0mm Package FDMF6708N

Typical Application Circuit

V5V

C

VDRV

DISB#

PWM Input

DISB#

PWM

OFF

ON

Open-Drain Output

ZCD_EN#

THWN#

DrMOS Block Diagram

C

VIN

VCIN

VDRV

FDMF6708N

CGND

PGND

VIN

R

BOOT

PHASE

VSWH

BOOT

C

BOOT

Figure 1. Typical Application Circuit

VIN 3V ~ 24V

L

OUT

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

V

OUT

C

OUT

VCIN

DISB#

PWM

THWN#

R

UP_PWM

R

DN_PWM

10µA

UVLO

V

CIN

Temp.

Sense

Input

3- State

Logic

VDRV

BOOT

VIN

Q1 HS Power MOSFET

GH

Logic

D

Level-Shift

Boot

GH

20kΩ

PHASE

Dead-Time

Control

V

DRV

GL

Logic

V

CIN

GL

VSWH

Q2 LS Power MOSFET

10µA

CGND

ZCD_EN#

PGND

Figure 2. DrMOS Block Diagram

Pin Configuration

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Figure 3. Bottom View Figure 4. Top View

Pin Definitions

Pin # Name Description

When ZCD_EN#=HIGH, the low-side driver is the inverse of the PWM input. When

1 ZCD_EN#

2 VCIN IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND.

3 VDRV

4 BOOT

5, 37, 41 CGND IC ground. Ground return for driver IC.

6 GH For manufacturing test only. This pin must float; it must not be connected to any pin.

7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

8 NC

9 - 14, 42 VIN Power input. Output stage supply voltage.

15, 29 -

35, 43

16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET.

36 GL For manufacturing test only. This pin must float; it must not be connected to any pin.

38 THWN#

39 DISB#

40 PWM PWM signal input. This pin accepts a three-state 5V PWM signal from the controller.

VSWH

ZCD_EN#=LOW, diode emulation is enabled. This pin has a 10µA internal pull-up current source. Do not add a noise filter capacitor.

Power for the gate driver. Minimum 1µF ceramic capacitor is recommended to be connected as close as possible from this pin to CGND.

Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE.

No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience.

Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module.

Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor.

Absolute Maximum Ratings

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

V

Supply Voltage Referenced to CGND -0.3 7.0 V

CIN

V

Drive Voltage Referenced to CGND -0.3 7.0 V

DRV

V

Output Disable Referenced to CGND -0.3 7.0 V

DISB#

V

PWM Signal Input Referenced to CGND -0.3 7.0 V

PWM

V

Note:

1. I

ZCD Enable Signal Input Referenced to CGND -0.3 7.0 V

ZCD_EN#

VGL Low Gate Manufacturing Test Pin Referenced to CGND -0.3 7.0 V

Thermal Warning Flag Referenced to CGND -0.3 7.0 V

THWN#

VIN Power Input Referenced to PGND, CGND -0.3 30.0 V

V

Bootstrap Supply

BOOT

VGH High Gate Manufacturing Test Pin

V

PHASE Referenced to CGND -0.3 30.0 V

PHS

V

Switch Node Input

SWH

V

Bootstrap Supply

BOOT

I

THWN# Sink Current -0.1 7.0 mA

THWN#

I

O(AV)

θ

JPCB

Output Current

Junction-to-PCB Thermal Resistance 3.5 °C/W

(1)

Referenced to VSWH, PHASE -0.3 7.0 V

Referenced to CGND -0.3 30.0 V

Referenced to VSWH, PHASE -0.3 7.0 V

Referenced to CGND -0.3 30.0 V

Referenced to PGND, CGND (DC Only) -0.3 30.0 V

Referenced to PGND,<20ns -8.0 33.0 V

Referenced to VDRV 22.0 V

Referenced to VDRV,<20ns 25.0 V

f

=300kHz, VIN=12V, VO=1.0V 50

SW

fSW=1MHz, VIN=12V, VO=1.0V 45

TA Ambient Temperature Range -40 +125 °C

TJ Maximum Junction Temperature +150 °C

T

Storage Temperature Range -55 +150 °C

STG

ESD Electrostatic Discharge Protection

is rated using Fairchild’s DrMOS evaluation board, at TA = 25°C, with natural convection cooling. This rating

O(AV)

is limited by the peak DrMOS temperature, T

Human Body Model, JESD22-A114 2000

Charged Device Model, JESD22-C101 2500

= 150°C, and varies depending on operating conditions and PCB

J

layout. This rating can be changed with different application settings.

A

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

V

Control Circuit Supply Voltage 4.5 5.0 5.5 V

CIN

V

Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V

DRV

VIN Output Stage Supply Voltage 3.0 12.0 24.0

Note:

2. Operating at high V

can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes

IN

during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must

remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.

(2)

V

Electrical Characteristics

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Basic Operation

IQ Quiescent Current IQ=I

V

UVLO Threshold V

UVLO

V

UVLO_Hys

PWM Input (V

R

V

t

D_HOLD-OFF

V

t

PWM-OFF_MIN

PWM Input (V

R

V

t

D_HOLD-OFF

V

t

PWM-OFF_MIN

DISB# Input

V

t

PD_DISBL

t

PD_DISBH

ZCD_EN# Input

V

IH_ZCD_EN

V

IL_ZCD_EN

t

PD_ZLGLL

t

PD_ZHGLH

UVLO Hysteresis 0.35 V

= V

CIN

Pull-Up Impedance V

UP_PWM

Pull-Down Impedance V

DN_PWM

PWM High Level Voltage 3.15 3.80 4.45 V

IH_PWM

3-State Upper Threshold 3.10 3.75 4.40 V

TRI_HI

3-State Lower Threshold 1.05 1.40 1.90 V

TRI_LO

PWM Low Level Voltage 0.70 1.00 1.30 V

IL_PWM

= 5V ±10%)

DRV

3-State Shut-Off Time 150 ns

3-State Open Voltage 2.20 2.50 2.80 V

HiZ_PWM

PWM Minimum Off Time 70 ns

= V

CIN

Pull-Up Impedance V

UP_PWM

Pull-Down Impedance V

DN_PWM

PWM High Level Voltage 3.35 3.80 4.25 V

IH_PWM

3-State Upper Threshold 3.30 3.75 4.20 V

TRI_HI

3-State Lower Threshold 1.10 1.40 1.75 V

TRI_LO

PWM Low Level Voltage 0.74 1.00 1.26 V

IL_PWM

= 5V ±5%)

DRV

3-State Shut-Off Time 150 ns

3-State Open Voltage 2.30 2.50 2.70 V

HiZ_PWM

PWM Minimum Off Time 70 ns

High-Level Input Voltage 2 V

IH_DISB

Low-Level Input Voltage 0.8 V

IL_DISB

I

Pull-Down Current 10 µA

PLD

Propagation Delay

High-Level Input Voltage 2 V

Low-Level Input Voltage 0.8 V

I

Pull-Up Current 10 µA

PLU

Propagation Delay

= 5V, V

CIN

= 5V, and TA = T

DRV

VCIN+IVDRV

Rising 3.3 V

CIN

=5V 20 kΩ

PWM

=0V 20 kΩ

PWM

=5V 20 kΩ

PWM

=0V 20 kΩ

PWM

PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH

= +25°C unless otherwise noted.

J

, PWM=LOW or HIGH or Float 2 mA

220 ns

520 ns

PWM=GND, Delay Between ZCD_EN# from HIGH to LOW to GL from HIGH to

1800 ns

LOW

PWM=GND, Delay Between ZCD_EN# from LOW to HIGH to GL from LOW to

20 ns

HIGH

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Continued on the following page…

Electrical Characteristics

Typical values are VIN = 12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Thermal Warning Flag

T

Activation Temperature 150 °C

ACT

T

Reset Temperature 135 °C

RST

R

Pull-Down Resistance 5kΩ resistor pull-up to V

THWN

High-Side Driver (fSW = 1000kHz, I

R

SOURCE_GH

R

SINK_GH

t

D_DEADON

t

PD_PLGHL

t

PD_PHGHH

t

PD_TSGHH

Output Impedance, Sourcing Source Current=50mA 0.8 Ω

Output Impedance, Sinking Sink Current=50mA 0.6 Ω

Rise Time GH=10% to 90% 10 ns

R_GH

Fall Time GH=90% to 10% 10 ns

F_GH

LS to HS Deadband Time

PWM LOW Propagation Delay

PWM HIGH Propagation Delay (ZCD_EN# =0)

Exiting 3-State Propagation Delay

= 5V, V

CIN

= 5V, and TA = T

DRV

= 30A, TA = +25°C)

OUT

GL Going LOW to GH Going HIGH,

1.7V GL to 10% GH

PWM Going LOW to GH Going LOW, V

IL_PWM

to 90% GH

PWM Going HIGH to GH Going HIGH, V

IH_PWM

PWM (From 3-State) Going HIGH to GH Going HIGH, V

= +25°C unless otherwise noted.

J

60 Ω

CIN

to 10% GH (ZCD_EN# =0, I

to 10% GH

IH_PWM

D_LS

>0)

20 ns

25 ns

35 ns

FDMF6708N — Extra-Small, High-Performance, High-Frequency DrMOS Module

Low-Side Driver (fSW = 1000kHz, I

R

SOURCE_GL

R

SINK_GL

t

D_DEADOFF

t

PD_PHGLL

t

PD_TSGLH

t

GL-ON_MIN

Output Impedance, Sourcing Source Current=50mA 0.9 Ω

Output Impedance, Sinking Sink Current=50mA 0.4 Ω

Rise Time GL=10% to 90% 20 ns

R_GL

Fall Time GL=90% to 10% 10 ns

F_GL

HS to LS Deadband Time

PWM-HIGH Propagation Delay

Exiting 3-State Propagation Delay

GL Minimum On Time in DCM

= 30A, TA = +25°C)

OUT

SW Going LOW to GL Going HIGH,

1.7V SW to 10% GL

PWM Going HIGH to GL Going LOW, V

IH_PWM

PWM (From 3-State) Going LOW to GL Going HIGH, V

V

ZCD_EN#

20 ns

to 90% GL

IL_PWM

to 10% GL

20 ns

30 ns

=0V 350 ns

Boot Diode

VF Forward-Voltage Drop IF=1mA 0.6 V

VR Breakdown Voltage IR=1mA 22 V