Under-Voltage Lockout (UVLO)
Optimized for Switching Frequencies up to 1MHz
Low-Profile SMD Package
Fairchild Green Packaging and RoHS Compliant
Based on the Intel® 4.0 DrMOS Standard
Description
The XS™ DrMOS family is Fairchild’s next-generation,
fully optimized, ultra-compact, integrated MOSFET plus
driver power stage solutions for high-current, highfrequency, synchronous buck DC-DC applications. The
FDMF6706C integrates a driver IC, two power
MOSFETs, and a bootstrap Schottky diode into a
thermally enhanced, ultra-compact 6x6mm PQFN
package.
With an integrated approach, the complete switching
power stage is optimized with regards to driver and
MOSFET dynamic performance, system inductance,
and Power MOSFET R
Fairchild's high-performance PowerTrench® MOSFET
technology, which dramatically reduces switch ringing,
eliminating the need for a snubber circuit in most buck
converter applications.
A new driver IC with reduced dead times and
propagation delays further enhances the performance of
this part. A thermal warning function has been included
to warn of a potential over-temperature situation. The
FDMF6706C also incorporates features, such as Skip
Mode (SMOD), for improved light-load efficiency along
with a 3-state 5V PWM input for compatibility with a
wide range of PWM controllers.
16 – 28 PGND Power ground. Output stage ground. Source pin of low-side MOSFET.
36 GL For manufacturing test only. This pin must float. Must not be connected to any pin.
38 THWN#
39 DISB#
40 PWM PWM signal input. This pin accepts a 3-state 5VPWM signal from the controller.
VSWH
the low-side driver is disabled. This pin has a 10µA internal pull-up current source. Do not add a
noise filter capacitor.
Power for gate driver. Minimum 1µF ceramic capacitor is recommended to be connected as
close as possible from this pin to CGND.
Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect
bootstrap capacitor from this pin to PHASE.
No connect. The pin is not electrically connected internally, but can be connected to VIN for
convenience.
Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point
for the adaptive shoot-through protection.
Thermal warning flag, open collector output. When temperature exceeds the trip limit, the
output is pulled LOW. THWN# does not disable the module.
Output disable. When LOW, this pin disables Power MOSFET switching (GH and GL are held
LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter
capacitor.
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Operating and Storage Temperature Range -55 +150 °C
ESD Electrostatic Discharge Protection
SW
fSW=1MHz 40
Human Body Model, JESD22-A114 2000
Charged Device Model, JESD22-C1012000
Note:
1. I
is rated using Fairchild’s DrMOS evaluation board, at TA = 25°C, with natural convection cooling. This rating
O(AV)
is limited by the peak DrMOS temperature, T
= 150°C, and varies depending on operating conditions and PCB
J
layout. This rating can be changed with different application settings.
V
A
V
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol Parameter Min. Typ. Max. Unit
V
Control Circuit Supply Voltage 4.5 5.0 5.5 V
CIN
V
Gate Drive Circuit Supply Voltage 4.5 5.0 5.5 V
DRV
VIN Output Stage Supply Voltage
Note:
2. Operating at high V
can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes
IN
during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must
remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.