Fairchild FDMF6705V service manual

March 2012

FDMF6705V - Extra-Small, High-Performance, HighFrequency DrMOS Module

Benefits

 Single 12V Input Power Supply Operation  Ultra-Compact 6x6mm PQFN, 72% Space-Saving

Compared to Conventional Discrete Solutions

 Fully Optimized System Efficiency  Clean Switching Waveforms with Minimal Ringing  High-Current Handling

Features

 Over 93% Peak-Efficiency  High-Current Handling of 43A  High-Performance PQFN Copper Clip Package  3-State 5V PWM Input Driver  Shorter Propagation Delays than FDMF6704V  Shorter Dead Times than FDMF6704V  Skip-Mode SMOD# (Low-Side Gate Turn Off) Input  Thermal Warning Flag for Over-Temperature

Condition

 Driver Output Disable Function (DISB# Pin)  Internal Pull-Up and Pull-Down for SMOD# and

DISB# Inputs, Respectively

 Fairchild PowerTrench® Technology MOSFETs for

Clean Voltage Waveforms and Reduced Ringing

 Fairchild SyncFET™ (Integrated Schottky Diode)

Technology in the Low-Side MOSFET

 Integrated Bootstrap Schottky Diode  Adaptive Gate Drive Timing for Shoot-through

Protection

 Under-Voltage Lockout (UVLO)  Optimized for Switching Frequencies up to 1MHz  Low-Profile SMD Package  Fairchild Green Packaging and RoHS Compliant  Based on the Intel® 4.0 DrMOS Standard

Description

The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, ultra-compact, integrated MOSFET plus driver power stage solutions for high-current, high-frequency, synchronous buck DC-DC applications. The FDMF6705V integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6mm PQFN package.

With an integrated approach, the complete switching power stage is optimized with regards to driver and MOSFET dynamic performance, system inductance, and Power MOSFET R Fairchild's high-performance PowerTrench® MOSFET technology, which dramatically reduces switch ringing, eliminating the need for a snubber circuit in most buck converter applications.

A new driver IC with reduced dead times and propagation delays further enhances the performance of this part. A thermal warning function has been included to warn of a potential over-temperature situation. The FDMF6705V also incorporates features, such as Skip Mode (SMOD), for improved light-load efficiency along with a 3-state PWM input for compatibility with a wide range of PWM controllers.

. XS™ DrMOS uses

DS(ON)

Applications

High-Performance Gaming Motherboards

  Compact Blade Servers, V-Core and Non-V-Core

DC-DC Converters

 Desktop Computers, V-Core and Non-V-Core

DC-DC Converters

 Workstations  High-Current DC-DC Point-of-Load (POL)

Converters

 Networking and Telecom Microprocessor Voltage

Regulators

 Small Form-Factor Voltage Regulator Modules

FDMF6705V - Extra-Small High-Performance, High-Frequency DrMOS Module

Ordering Information

Part

Number

FDMF6705V 40A 12V 1000kHz

Current

Rating

Input

Voltage

Switching

Frequency

Package Top Mark

40-Lead, Clipbond PQFN DrMOS,

6.0x6.0mm Package

FDMF6705V

Typical Application Circuit

t

V

FDMF6705V - Extra-Small High-Performance, High-Frequency DrMOS Module

V

CIN

V

=3V to15 V

IN

V

DRV

=8V to 15 V

C

VDRV

C

VCI

PWM

Control

Enable

OFF

Disabled ON

DrMOS Block Diagram

VDRV VIN

THWN#

VDRV

VCIN

CGND

PWM

SMOD #

DISB #

5

Linear

Reg

Temp Sense

.

Control

D

Boo

HDRV

V

CIN

LDRV

CGND

Figure 1. Typical Application Circuit

VCIN

VIN

PGND

C

VIN

BOOT

Q1

PHASE

VSWH

L

OUT

C

OUT

V

OUT

Q2

BOOT

GL

30kΩ

PGND

Q1 HS Power MOSFET

Q2 LS Power MOSFET

PHASE

VSWH

DISB#

PWM

THWN#

VCC UVLO

R

DN_PWM

CGND

UP_PWM

10µA

V

VIN UVLO

CIN

Temp. Sense

Input

-State

3

Logic

5V LDO

V

CIN

SMOD#

10µA

GH

Logic

GL

Logic

Level Shift

Dead-Time

Control

D

Boot

GH

V

CIN

Figure 2. DrMOS Block Diagram

Pin Configuration

FDMF6705V - Extra-Small High-Performance, High-Frequency DrMOS Module

Figure 3. Bottom View Figure 4. Top View

Pin Definitions

Pin # Name Description

When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW,

1 SMOD#

2 VCIN

3 VDRV

4 BOOT

5, 37, 41 CGND IC ground. Ground return for driver IC.

6 GH For manufacturing test only. This pin must float. Must not be connected to any pin.

7 PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.

8 NC

9 - 14, 42 VIN Power input. Output stage supply voltage.

15, 29 -

35, 43

16 – 28 PGND Power ground. Output stage ground. Source pin of low-side MOSFET.

36 GL For manufacturing test only. This pin must float. Must not be connected to any pin.

38 THWN#

39 DISB#

40 PWM

VSWH

the low-side driver is disabled. This pin has a 10µA internal pull-up current source. Do not add a noise filter capacitor.

Linear regulator 5V output. IC bias supply for gate drive output stage. Minimum 1µF ceramic capacitor is required and should be connected as close as possible from this pin to CGND

Linear regulator input. Minimum 1µF ceramic capacitor is recommended and should be connected as close as possible from this pin to CGND.

Bootstrap supply input. Provides voltage supply to high-side MOSFET driver. Connect bootstrap capacitor from this pin to PHASE.

No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience.

Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection.

Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module.

Output disable. When LOW, this pin disables Power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor.

PWM signal input. This pin accepts a 3-state logic-level PWM signal from the controller.

FDMF6705V - Extra-Small High-Performance, High-Frequency DrMOS Module

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VCIN, DISB#, PWM, SMOD#, GL, THWN# to CGND Pins 6

VIN to PGND, CGND Pins 25

VDRV to PGND, CGND 16

BOOT, GH to VSWH, PHASE Pins 6

BOOT, VSWH, PHASE, GH to GND Pins 25

BOOT to VCIN Pins 22

f

=300kHz 43

(1)

I

O(AV)

θ

T

JPCB

STG

=12V, VO=1.0V

VIN

Junction-to-PCB Thermal Resistance 3.5 °C/W

Operating and Storage Temperature Range -55 +150 °C

ESD Electrostatic Discharge Protection

SW

fSW=1MHz 40

Human Body Model, JESD22-A114 2000

Charged Device Model, JESD22-C101 2000

Note:

1. I

is rated using Fairchild’s DrMOS evaluation board, TA = 25°C, natural convection cooling. This rating is limited

O(AV)

by the peak DrMOS temperature, T

= 150°C, and varies depending on operating conditions and PCB layout. This

J

rating can be changed with different application settings.

V

A

V

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

V

Gate Drive Control Circuit Input Supply Voltage

DRV

VIN Output Stage Supply Voltage

(2)

Note:

2. Operating at high V

can create excessive AC overshoots on the VSWH-to-GND and BOOT-to-GND nodes

IN

during MOSFET switching transients. For reliable DrMOS operation, VSWH-to-GND and BOOT-to-GND must

remain at or below the Absolute Maximum Ratings shown in the table above. Refer to the “Application Information” and “PCB Layout Guidelines” sections of this datasheet for additional information.

8 12 15

3 12 15

V

Electrical Characteristics

Typical values are VIN=12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

I

Operating Current V

DRV

Internal 5V Linear Regulator

V

Input Voltage 8 12 14 V

DRV

I

Input Current 8V<VIN<14V, fSW=1MHz 36 mA

DRV

V

Output Voltage V

CIN

P

Power Dissipation V

VDRV

C

VCIN Bypass Capacitor X7R or X5R Ceramic 1 10 µF

VCIN

V

Line Regulation 8V<VIN<14V, I

RLINE

V

Load Regulation V

RLOAD

Short-Circuit Current Limit 200 mA

UVLO UVLO Threshold V

UVLO

PWM Input

R

UP_PWM

R

Down_PWM

V

t

D_HOLD-OFF

V

HiZ_PWM

DISB# Input

V

t

PD_DISBL

t

PD_DISBH

SMOD# Input

V

IH_SMOD

V

IL_SMOD

t

PD_SLGLL

t

PD_SHGLH

UVLO Hysteresis 0.435 V

_Hyst

Pull-Up Impedance 10 kΩ

Pull-Down Impedance 10 kΩ

PWM High Level Voltage 3.30 3.55 3.80 V

IH_PWM

3-State Rising Threshold 3.20 3.45 3.70 V

TRI_HI

3-State Falling Threshold 1.00 1.25 1.50 V

TRI_LO

PWM Low Level Voltage 0.85 1.15 1.40 V

IL_PWM

3-State Shutoff Time 160 200 ns

3-State Open Voltage 2.3 2.5 2.7 V

High-Level Input Voltage 2 V

IH_DISB

Low-Level Input Voltage 0.8 V

IL_DISB

I

Pull-Down Current 10 µA

PLD

Propagation Delay

High-Level Input Voltage 2 V

Low-Level Input Voltage 0.8 V

I

Pull-Up Current 10 µA

PLM

Propagation Delay

=12V, and TA=+25°C unless otherwise noted.

DRV

=14V, PWM=LOW or HIGH or Float 2 5 mA

DRV

=8V, I

DRV

=12V, fSW=1MHz 250 mW

DRV

=8V, 5mA<I

DRV

Rising 6.8 7.3 7.8 V

DRV

=5mA 4.8 5.0 5.2 V

LOAD

=5mA 20 mV

LOAD

<100mA 75 mV

LOAD

PWM=GND, Delay Between DISB# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between DISB# from LOW to HIGH to GL from LOW to HIGH

PWM=GND, Delay Between SMOD# from HIGH to LOW to GL from HIGH to LOW

PWM=GND, Delay Between SMOD# from LOW to HIGH to GL from LOW to HIGH

25 ns

10 ns

Continued on the following page…

FDMF6705V - Extra-Small High-Performance, High-Frequency DrMOS Module

Electrical Characteristics (Continued)

Typical values are VIN=12V, V

Symbol Parameter Condition Min. Typ. Max. Unit

Thermal Warning Flag

T

Activation Temperature 150 °C

ACT

T

Reset Temperature 135 °C

RST

R

Pull-Down Resistance I

THWN

250ns Timeout Circuit

t

D_TIMEOUT

High-Side Driver

R

SOURCE_GH

R

t

D_DEADON

t

PD_PLGHL

t

PD_PHGHH

t

PD_TSGHH

Low-Side Driver

R

SOURCE_GL

R

t

D_DEADOFF

t

PD_PHGLL

t

PD_TSGLH

Boot Diode

Timeout Delay

Output Impedance, Sourcing Source Current=100mA 1 Ω

SINK_GH

t

R_GH

t

F_GH

SINK_GL

t

R_GL

t

F_GL

VF

VR

Output Impedance, Sinking Sink Current=100mA 0.8 Ω

Rise Time GH=10% to 90%, C

Fall Time GH=90% to 10%, C

LS to HS Deadband Time

PWM LOW Propagation Delay

PWM HIGH Propagation Delay (SMOD Held LOW)

Exiting 3-State Propagation Delay

Output Impedance, Sourcing Source Current=100mA 1 Ω

Output Impedance, Sinking Sink Current=100mA 0.5 Ω

Rise Time GL=10% to 90%, C

Fall Time GL=90% to 10%, C

HS to LS Deadband Time

PWM-HIGH Propagation Delay

Exiting 3-State Propagation Delay

Forward-Voltage Drop I

Breakdown Voltage I

=12V, and TA=+25°C unless otherwise noted.

DRV

=5mA 30 Ω

PLD

SW=0V, Delay Between GH from HIGH to LOW and GL from LOW to HIGH

=1.1nF 12 ns

LOAD

=1.1nF 11 ns

LOAD

GL going LOW to GH going HIGH, 2V GL to 10 % GH

PWM going LOW to GH going LOW, V

to 90% GH

IL_PWM

PWM Going HIGH to GH going HIGH, V

to 10% GH (SMOD=LOW)

IH_PWM

PWM (from 3-State) going HIGH to GH going HIGH, V

IH_PWM

to 10% GH

=2.7nF 12 ns

LOAD

=2.7nF 8 ns

LOAD

SW going LOW to GL going HIGH,

2.2V SW to 10% GL

PWM going HIGH to GL going LOW, V

IH_PWM

to 90% GL

PWM (from 3-State) going LOW to GL going HIGH, V

=10mA 0.35 V

F

=1mA 22 V

R

IL_PWM

to 10% GL

250 ns

10 ns

16 30 ns

30 ns

12 ns

9 25 ns

20 ns

FDMF6705V - Extra-Small High-Performance, High-Frequency DrMOS Module