FDMA1024NZ
Dual N-Channel PowerTrench
20 V, 5.0 A, 54 mΩ
Features
Max r
Max r
Max r
Max r
HBM ESD protection level = 1.6 kV (Note 3)
Low profile - 0.8 mm maximum - in the new package
MicroFET 2x2 mm
RoHS Compliant
Free from halogenated compounds and antimony
oxides
= 54 mΩ at VGS = 4.5 V, ID = 5.0 A
DS(on)
= 66 mΩ at VGS = 2.5 V, ID = 4.2 A
DS(on)
= 82 mΩ at VGS = 1.8 V, ID = 2.3 A
DS(on)
= 114 mΩ at VGS = 1.5 V, ID = 2.0 A
DS(on)
®
MOSFET
General Description
This device is designed specifically as a single package solution
for dual switching requirements in cellular handset and other
ultr
N-Channel MOSFETs wi
conduction losses.
The MicroFET 2X2 package offers exceptional thermal
performance for its physical size and is well suited to linear mo de
applications.
Applications
Baseband Switch
Loadswitch
DC-DC Conversion
a-portable applications. It features two
FDMA1024NZ Dual N-Channel Power Trench
May 2010
independent
th low on-state resistance for minimum
®
MOSFET
PIN 1
MicroFET 2x2
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
P
D
, T
T
J
STG
Drain to Source Voltage 20 V
Gate to Source Voltage ±8 V
Drain Current -Continuous (Note 1a) 5.0
-Pulsed 6.0
Power Dissipation (Note 1a) 1.4
Power Dissipation (Note 1b) 0.7
Operating and Storage Junction Temperature Range –55 to +150 °C
S1 G1 D2
D1 D2
D1 G2
= 25 °C unless otherwise noted
A
S2
S1
G1
D2
1
2
3
6
5
4
Thermal Characteristics
R
θJA
R
θJA
R
θJA
R
θJA
Thermal Resistance, Junction to Ambient (Note 1a) 86 (Single Operation)
Thermal Resistance, Junction to Ambient (Note 1b) 173 (Single Operation)
Thermal Resistance, Junction to Ambient (Note 1c) 69 (Dual Operation)
Thermal Resistance, Junction to Ambient (Note 1d) 151 (Dual Operation)
Package Marking and Ordering Information
D1
G2
S2
A
W
°C/W
Device Marking Device Package Reel Size Tape Width Quantity
024 FDMA1024NZ MicroFET 2X2 7 ” 8 mm 3000 units
©2010 Fairchild Semiconductor Corporation
FDMA1024NZ Rev.B4
1
www.fairchildsemi.com
FDMA1024NZ Dual N-Channel Power Trench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
∆BV
∆T
I
DSS
I
GSS
DSS
DSS
J
Drain to Source Breakdown Voltage ID = 250 µA, VGS = 0 V 20 V
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current VDS = 16 V, V
Gate to Source Leakage Current VGS = ±8 V, V
I
= 250 µA, referenced to 25 °C 19 mV/°C
D
= 0 V 1 µA
GS
= 0 V ±10 µA
DS
On Characteristics
V
GS(th)
∆V
∆T
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage VGS = VDS, ID = 250 µA 0.4 0.7 1.0 V
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On-Resistance
= 250 µA, referenced to 25 °C -3 mV/°C
I
D
V
= 4.5 V, ID = 5.0 A 37 54
GS
= 2.5 V, ID = 4.2 A 43 66
V
GS
= 1.8 V, ID = 2.3 A 52 82
V
GS
= 1.5 V, ID = 2.0 A 67 114
V
GS
= 4.5 V, ID = 5.0 A, TJ = 125 °C 51 75
V
GS
Forward Transconductance VDD = 5 V, ID = 5.0 A 16 S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
G
Input Capacitance
Output Capacitance 70 95 pF
Reverse Transfer Capacitance 40 65 pF
= 10 V, VGS = 0 V,
V
DS
f = 1 MHz
Gate Resistance f = 1 MHz 4.3 Ω
375 500 pF
mΩ
®
MOSFET
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
g
gs
gd
Turn-On Delay Time
Rise Time 2.2 10 ns
Turn-Off Delay Time 18 33 ns
Fall Time 2.3 10 ns
Total Gate Charge
Gate to Source Gate Charge 0.6 nC
Gate to Drain “Miller” Charge 0.9 nC
Drain-Source Diode Characteristics
I
S
V
SD
t
rr
Q
rr
Maximum Continuous Source-Drain Diode Forward Current
Source to Drain Diode Forward Voltage V
Reverse Recovery Time
Reverse Recovery Charge 5 10 nC
5.3 11 ns
V
= 10 V, ID = 5.0 A
DD
= 4.5 V, R
V
GS
V
= 4.5 V, VDD = 10 V,
GS
= 5.0 A
I
D
GEN
= 6 Ω
5.2 7.3 nC
1.1
= 0 V, IS = 1.1 A (Note 2) 0.7 1.2 V
GS
= 5.0 A, di/dt = 100 A/µs
I
F
19 35 ns
A
©2010 Fairchild Semiconductor Corporation
FDMA1024NZ Rev.B4
2
www.fairchildsemi.com
Notes:
1. R
is determined with the device mounted on a 1 in2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJA
user's board design.
(a) R
(b) R
(c) R
(d) R
= 86 °C/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation.
θJA
= 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation.
θJA
= 69 oC/W when mounted on a 1 in2 pad of 2 oz copper, 1.5 ” x 1.5 ” x 0.062 ” thick PCB. For dual operation.
θJA
= 151 oC/W when mounted on a minimum pad of 2 oz copper. For dual operation.
θJA
is guaranteed by design while R
θJC
is determined by the
θJA
FDMA1024NZ Dual N-Channel Power Trench
o
a) 86
C/W when
mounted on a 1
in2 pad of 2 oz
copper.
2. Pulse Test : Pulse Width < 300 us, Duty Cycle < 2.0 %
3: The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
o
b) 173
C/W when
mounted on a
minimum pad of 2
oz copper.
c) 69
mounted on a 1
in2 pad of 2 oz
copper.
o
C/W when
o
d) 151
C/W when
mounted on a
minimum pad of 2
oz copper.
®
MOSFET
©2010 Fairchild Semiconductor Corporation
FDMA1024NZ Rev.B4
3
www.fairchildsemi.com
Typical Characteristics T
= 25 °C unless otherwise noted
J
FDMA1024NZ Dual N-Channel Power Trench
6
5
4
3
VGS = 4.5 V
VGS = 3.5 V
VGS = 2.5 V
VGS = 1.8 V
VGS = 1.5 V
2
DRAIN CURRENT (A)
,
D
I
1
0
0.0 0.2 0.4 0.6 0.8 1.0
Figure 1.
1.6
1.4
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
V
,
DRAIN TO SOURCE VOLTAGE (V)
DS
On-Region Characteristics Figure 2.
ID = 5 A
= 4.5 V
V
GS
1.2
1.0
NORMALIZED
0.8
DRAIN TO SOURCE ON-RESISTANCE
0.6
-75 -50 -25 0 25 50 75 100 125 150
T
,
JUNCTION TEMPERATURE
J
o
(
C
)
F i g u r e 3 . N o r m a l i z e d O n - R e s i s t a n c e
vs Junction Temperature
3.0
PULSE DURATION = 80 µs
2.5
DUTY CYCLE = 0.5% MAX
VGS = 1.5 V
2.0
V
GS
= 3.5 V
NORMALIZED
1.5
1.0
DRAIN TO SOURCE ON-RESISTANCE
0.5
123456
I
,
DRAIN CURRENT (A)
D
VGS = 1.8 V
V
GS
V
GS
N o r m a l i z e d O n - R e s i s t a n c e
vs Drain Current and Gate Voltage
200
)
Ω
m
160
(
120
DRAIN TO
,
80
DS(on)
r
40
SOURCE ON-RESISTANCE
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
,
GATE TO SOURCE VOLTAGE (V)
GS
Figure 4.
O n - R es i s t a n c e vs G a t e t o
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
ID = 2.5 A
TJ = 125 oC
TJ = 25 oC
Source Voltage
= 2.5 V
= 4.5 V
®
MOSFET
6
PULSE DURATION = 80 µs
DUTY CYCLE = 0.5% MAX
5
V
= 5 V
DS
4
3
TJ = 125 oC
2
, DRAIN CURRENT (A)
D
I
1
0
0.0 0.5 1.0 1.5 2.0
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
©2010 Fairchild Semiconductor Corporation
FDMA1024NZ Rev.B4
10
V
= 0 V
GS
1
0.1
TJ = 25 oC
TJ = -55 oC
0.01
, REVERSE DRAIN CURRENT (A)
S
I
1E-3
0.0 0.2 0.4 0.6 0.8 1.0 1.2
Figure 6.
TJ = 125 oC
TJ = 25 oC
TJ = -55 oC
VSD, BODY DIODE FORWARD VOLTAGE (V)
S o u r ce t o D r a i n D io d e
Forward Voltage vs Source Current
4
www.fairchildsemi.com
FDMA1024NZ Dual N-Channel Power Trench
Typical Characteristics T
5
ID = 5 A
4
3
V
= 8 V
DD
2
1
, GATE TO SOURCE VOLTAGE (V)
GS
V
0
Figure 7.
-2
10
-3
10
-4
10
-5
10
-6
10
-7
GATE LEAKAGE CURRENT (A)
10
,
g
I
-8
10
Figure 9.
0123456
Gate Charge Characteristics Figure 8 .
V
= 0 V
GS
03691215
V
GS
Gate Leakage Current vs Gate to Source
VDD = 12 V
Qg, GATE CHARGE (nC)
TJ = 125 oC
,
GATE TO SOURCE VOLTAGE (V)
Voltage
= 25 °C unless otherwise noted
J
VDD = 10 V
TJ = 25 oC
1000
C
iss
100
CAPACITANCE (pF)
f = 1 MHz
= 0 V
V
GS
10
0.1 1 10 20
VDS, DRAIN TO SOURCE VOLTAGE (V)
C
oss
C
rss
C a p a c i t a n c e v s D r a i n
to Source Voltage
10
100 us
1
THIS AREA IS
LIMITED BY r
0.1
, DRAIN CURRENT (A)
D
I
0.01
0.1 1 10
DS(on)
SINGLE PULSE
= MAX RATED
T
J
R
= 173 oC/W
θ
JA
T
= 25 oC
A
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 10. Forward Bias Safe Operating Area
1 ms
10 ms
100 ms
1 s
10 s
DC
®
MOSFET
60
100
10
1
, PEAK TRANSIENT POWER (W)
(PK)
P
0.3
-3
10
©2010 Fairchild Semiconductor Corporation
FDMA1024NZ Rev.B4
VGS = 4.5 V
-2
10
Figure 11.
SINGLE PULSE
R
θ
T
A
-1
10
t, PULSE WIDTH (sec)
0
10
1
10
Single Pulse Maximum Power Dissipation
5
= 173 oC/W
JA
= 25 oC
100 1000
www.fairchildsemi.com
FDMA1024NZ Dual N-Channel Power Trench
Typical Characteristics T
2
1
JA
θ
Z
0.1
IMPEDANCE,
NORMALIZED THERMAL
0.01
10
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
R
θ
-3
-2
10
Figure 12. Junction to Ambient Transient Thermal Response Curve
JA
= 25 °C unless otherwise noted
J
= 173 oC/W
-1
10
t, RECTANGULAR PULSE DURATION (sec)
P
DM
NOTES:
DUTY FACTOR: D = t1/t
PEAK TJ = PDM x Z
θJA
110
t
1
t
2
2
x R
+ T
θJA
A
100 1000
®
MOSFET
©2010 Fairchild Semiconductor Corporation
FDMA1024NZ Rev.B4
6
www.fairchildsemi.com
Dimensional Outline and Pad Layout
FDMA1024NZ Dual N-Channel Power Trench
®
MOSFET
©2010 Fairchild Semiconductor Corporation
FDMA1024NZ Rev.B4
7
www.fairchildsemi.com
TRADEMARKS
The following includes registered and unregistered tradema rks and service marks, owned by Fair child Semiconductor and/ or its global subsidiaries, and is no t
intended to be an exhaustive list of all such trademarks.
AccuPower™
Auto-SPM™
Build it Now™
CorePLUS™
CorePOWER™
CROSSVOLT™
CTL™
Current Transfer Logic™
DEUXPEED
Dual Cool™
EcoSPARK
EfficentMax™
ESBC™
Fairchild
Fairchild Semiconductor
FACT Quiet Series™
FACT
FAST
FastvCore™
FETBench™
FlashWriter
FPS™
®
®
®
tm
®
®
®
®
*
F-PFS™
®
FRFET
Global Power Resource
Green FPS™
Green FPS™ e-Series™
Gmax™
GTO™
IntelliMAX™
ISOPLANAR™
MegaBuck™
MICROCOUPLER™
MicroFET™
MicroPak™
MicroPak2™
MillerDrive™
®
MotionMax™
Motion-SPM™
OptiHiT™
OPTOLOGIC
OPTOPLANAR
®
tm
®
SM
®
PDP SPM™
Power-SPM™
PowerTrench
PowerXS™
Programmable Active Droop™
QFET
QS™
Quiet Series™
RapidConfigure™
Saving our world, 1mW/W/kW at a time™
SignalWise™
SmartMax™
SMART START™
SPM
STEALTH™
SuperFET™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SupreMOS™
SyncFET™
Sync-Lock™
®
®
™
®
®*
The Power Franchise
TinyBoost™
TinyBuck™
TinyCalc™
TinyLogic
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
TriFault Detect™
TRUECURRENT™*
µSerDes™
UHC
Ultra FRFET™
UniFET™
VCX™
VisualMax™
XS™
®
tm
®
®
®
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
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PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.
FDMA1024NZ Dual N-Channel Power Trench
®
MOSFET
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into t he body or (b ) support or sustain life,
and (c) whose failure to perform when properly used in acco rdance with
instructions for use provided in the labeling, can be reasonably
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
expected to result in a significant injury of the user.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative / In Design
Preliminary First Production
No Identification Needed Full Production
Obsolete Not In Production
©2010 Fairchild Semiconductor Corporation 8
FDMA1024NZ Rev.B4
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Datasheet contains preliminary data; supplement ary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
Datasheet contains final specifications. Fairchild Semiconduct or reserves the right to
make changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fai r child
Semiconductor. The datashe et is for reference information only.
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Rev. I48
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