Fairchild FDG8850NZ service manual
tm
FDG8850NZ
Dual N-Channel PowerTrench® MOSFET
30V,0.75A,0.4Ω
FDG8850NZ Dual N-Channel PowerTrench
April 2007
Features
Max r
Max r
Very low level gate drive requirements allowing operation
in 3V circuits(V
Very small package outline SC70-6
RoHS Compliant
= 0.4Ω at VGS = 4.5V, ID = 0.75A
DS(on)
= 0.5Ω at VGS = 2.7V, ID = 0.67A
DS(on)
<1.5V)
GS(th)
G2
D1
SC70-6
Pin 1
S2
D2
G1
S1
General Description
This dual N-Channel logic level enhancement mode field effect
transistors are produced using Fairchild’s proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This device
has been designed especially for low voltage applications as
a replacement for bipolar digital transistors and small signal
MOSFETs. Since bias resistors are not required, this dual digital
FET can replace several different digital transistors, with differ
ent bias resistor values.
S1
G1
D2
Q1
Q2
D1
G2
S2
-
®
MOSFET
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
P
D
, T
T
J
STG
Thermal Characteristics
R
θJA
R
θJA
Package Marking and Ordering Information
Device Marking Device Reel Size Tape Width Quantity
©2007 Fairchild Semiconductor Corporation
FDG8850NZ Rev.B
Drain to Source Voltage 30 V
Gate to Source Voltage ±12 V
Drain Current -Continuous 0.75
-Pulsed 2.2
Power Dissipation for Single Operation (Note 1a)
(Note 1b)
Operating and Storage Junction Temperature Range –55 to +150 °C
Thermal Resistance, Junction to Ambient Single operation (Note 1a) 350
Thermal Resistance, Junction to Ambient Single operation (Note 1b) 415
.50 FDG8850NZ 7” 8mm 3000 units
= 25°C unless otherwise noted
A
1
0.36
0.30
A
W
°C/W
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FDG8850NZ Dual N-Channel PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
ΔBV
DSS
ΔT
J
I
DSS
I
GSS
On Characteristics
V
GS(th)
ΔV
GS(th)
ΔT
J
r
DS(on)
g
FS
Drain to Source Breakdown Voltage ID = 250μA, VGS = 0V 30 V
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current VDS = 24V, V
ID = 250μA, referenced to 25°C 25 mV/°C
= 0V 1 μA
GS
Gate to Source Leakage Current VGS = ±12V, VDS= 0V ±10 μA
Gate to Source Threshold Voltage VGS = VDS, ID = 250μA 0.65 1.0 1.5 V
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance VDS = 5V, ID = 0.75A 3 S
ID = 250μA, referenced to 25°C –3.0 mV/°C
VGS = 4.5V, ID = 0.75A
VGS = 2.7V, ID = 0.67A
VGS = 4.5V, ID = 0.75A ,TJ = 125°C
0.25
0.29
0.36
0.4
0.5
0.6
Dynamic Characteristics
C
iss
C
oss
C
rss
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
g
Q
gs
Q
gd
Input Capacitance
V
Output Capacitance 20 30 pF
= 10V, VGS = 0V, f= 1MHZ
DS
90 120 pF
Reverse Transfer Capacitance 15 25 pF
(note 2)
Turn-On Delay Time
Rise Time 1 10 ns
Turn-Off Delay Time 9 18 ns
VDD = 5V, ID = 0.5A,
VGS = 4.5V,R
GEN
= 6Ω
4 10 ns
Fall Time 1 10 ns
Total Gate Charge
V
Gate to Source Charge 0.29 nC
=4.5V, VDD = 5V, ID = 0.75A
GS
1.03 1.44 nC
Gate to Drain “Miller” Charge 0.17 nC
Ω
®
MOSFET
Drain-Source Diode Characteristics
I
S
V
SD
Notes:
1. R
θJA
R
θJC
2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%.
©2007 Fairchild Semiconductor Corporation
FDG8850NZ Rev.B
Maximum Continuous Drain-Source Diode Forward Current 0.3 A
Source to Drain Diode Forward Voltage V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
is guaranteed by design while R
Scale 1:1 on letter size paper.
is determined by the user's board design.
θJA
a. 350°C/W when mounted on a
1 in
and Maximum Ratings
2
pad of 2 oz copper .
= 0V, IS = 0.3A (Note 2) 0.76 1.2 V
GS
b. 415°C/W when mounted on a minimum pad
of 2 oz copper.
2
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