Fairchild FDG8842CZ service manual
tm
FDG8842CZ
Complementary PowerTrench® MOSFET
Q1:30V,0.75A,0.4Ω; Q2:–25V,–0.41A,1.1Ω
FDG8842CZ Complementary PowerTrench
April 2007
Features
Q1: N-Channel
Max r
Max r
Q2: P-Channel
Max r
Max r
Very low level gate drive requirements allowing direct
operation in 3V circuits(V
Very small package outline SC70-6
RoHS Compliant
= 0.4Ω at VGS = 4.5V, ID = 0.75A
DS(on)
= 0.5Ω at VGS = 2.7V, ID = 0.67A
DS(on)
= 1.1Ω at VGS = –4.5V, ID = –0.41A
DS(on)
= 1.5Ω at VGS = –2.7V, ID = –0.25A
DS(on)
<1.5V)
GS(th)
S2
G2
D1
SC70-6
Pin 1
D2
G1
S1
General Description
These N & P-Channel logic level enhancement mode field effect
transistors are produced using Fairchild’s proprietary, high cell
density, DMOS technology. This very high density process is
especially tailored to minimize on-state resistance. This
device has been designed especially for low voltage applica
tions as a replacement for bipolar digital transistors and small
signal MOSFETs. Since bias resistors are not required, this dual
digital FET can replace several different digital transistors, with
different bias resistor values.
S1
G1
D2
Q1
Q2
D1
G2
S2
-
®
MOSFET
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
P
D
, T
T
J
STG
Thermal Characteristics
R
θJA
R
θJA
Package Marking and Ordering Information
Device Marking Device Reel Size Tape Width Quantity
©2007 Fairchild Semiconductor Corporation
FDG8842CZ Rev.B
Drain to Source Voltage 30 –25 V
Gate to Source Voltage ±12 –8 V
Drain Current -Continuous 0.75 –0.41
-Pulsed 2.2 –1.2
Power Dissipation for Single Operation (Note 1a)
(Note 1b)
Operating and Storage Junction Temperature Range –55 to +150 °C
Thermal Resistance, Junction to Ambient Single operation (Note 1a) 350
Thermal Resistance, Junction to Ambient Single operation (Note 1b) 415
.42 FDG8842CZ 7” 8mm 3000 units
= 25°C unless otherwise noted
A
1
0.36
0.30
A
W
°C/W
www.fairchildsemi.com
FDG8842CZ Complementary PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Typ e Min Typ Max Units
Off Characteristics
BV
ΔBV
ΔT
I
DSS
I
GSS
DSS
DSS
J
Drain to Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
On Characteristics
V
GS(th)
ΔV
ΔT
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On
Resistance
Forward Transconductance
ID = 250μA, VGS = 0V
ID = –250μA, VGS = 0V
ID = 250μA, referenced to 25°C
ID = –250μA, referenced to 25°C
VDS = 24V, V
VDS = –20V, V
GS
GS
= 0V
= 0V
VGS = ±12V, VDS= 0V
VGS = –8V, VDS= 0V
VGS = VDS, ID = 250μA
VGS = VDS, ID = –250μA
ID = 250μA, referenced to 25°C
ID = –250μA, referenced to 25°C
VGS = 4.5V, ID = 0.75A
VGS = 2.7V, ID = 0.67A
VGS = 4.5V, ID = 0.75A ,TJ = 125°C
VGS = –4.5V, ID = –0.41A
VGS = –2.7V, ID = –0.25A
VGS = –4.5V, ID = –0.41A ,TJ = 125°C
VDS = 5V, ID = 0.75A
VDS = –5V, ID = –0.41A
Q1Q2 30
–25
Q1
Q2
Q1
Q2
Q1
Q2
Q1Q20.65
–0.65
Q1
Q2
Q1
Q2
Q1
Q2
V
25
–21
1.0
–0.8
–3.0
1.8
0.25
0.29
0.36
0.87
1.20
1.22
3
8
mV/°C
1
–1
±10
–100μAnA
1.5
–1.5
mV/°C
0.4
0.5
0.6
1.1
1.5
1.9
μA
Ω
S
V
®
MOSFET
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
g
gs
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
(note 2)
Q1
V
= 10V, VGS = 0V, f= 1MHZ
DS
Q2
V
= –10V, VGS = 0V, f= 1MHZ
DS
Q1
VDD = 5V, ID = 0.5A,
VGS = 4.5V,R
Q2
GEN
= 6Ω
VDD = –5V, ID = –0.5A,
VGS = –4.5V,R
GEN
= 6Ω
Q1
V
=4.5V, VDD = 5V, ID = 0.75A
GS
Q2
V
= –4.5V, VDD = –5V, ID = –0.41A
GS
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
90
70
20
30
15
15
120
100
30
40
25
25
4
10
6
12
1
10
29
9
18
56
1
10
64
1.44
1.68
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
16
35
40
1.03
1.20
0.29
0.31
0.17
0.22
©2007 Fairchild Semiconductor Corporation
FDG8842CZ Rev.B
2
www.fairchildsemi.com
FDG8842CZ Complementary PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
1. R
θJA
R
θJC
2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%.
Maximum Continuous Drain-Source Diode Forward Current
V
= 0V, IS = 0.3A (Note 2)
Source to Drain Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
is guaranteed by design while R
Scale 1:1 on letter size paper.
is determined by the user's board design.
θJA
a. 350°C/W when mounted on a
1 in2 pad of 2 oz copper .
GS
V
= 0V, IS = –0.3A (Note 2) Q1Q2
GS
Q1
Q2
0.76
–0.84
b. 415°C/W when mounted on a minimum pad
of 2 oz copper.
0.3
–0.3
1.2
–1.2
A
V
®
MOSFET
©2007 Fairchild Semiconductor Corporation
FDG8842CZ Rev.B
3
www.fairchildsemi.com
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