Fairchild FDG6304P service manual
FDG6304P
Dual P-Channel, Digital FET
General Description Features
These dual P-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
SC70-6
SOT-23
SuperSOTTM-6
July 1999
-25 V, -0.41 A continuous, -1.5 A peak.
R
R
Very low level gate drive requirements allowing direct
operation in 3 V circuits (V
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
SuperSOTTM-8
= 1.1 Ω @ VGS= -4.5 V,
DS(ON)
= 1.5 Ω @ VGS= -2.7 V.
DS(ON)
< 1.5 V).
GS(th)
SO-8
SOT-223
S2
1 or 4
2 or 5
*
6 or 3
5 or 2
D1
G2
.04
D2
SC70-6
*The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings T
Symbol Parameter FDG6304P Units
V
DSS
V
GSS
I
D
P
D
TJ,T
ESD Electrostatic Discharge Rating MIL-STD-883D
THERMAL CHARACTERISTICS
R
JA
θ
Drain-Source Voltage -25 V
Gate-Source Voltage -8 V
Drain/Output Current - Continuous -0.41 A
Maximum Power Dissipation (Note 1) 0.3 W
Operating and Storage Temperature Range -55 to 150 °C
STG
Human Body Model (100 pF / 1500 Ω)
Thermal Resistance, Junction-to-Ambient (Note 1) 415 °C/W
G1
S1
3 or 6
= 25°C unless otherwise noted
A
- Pulsed -1.5
6.0 kV
4 or 1
*
FDG6304P Rev.E1
Electrical Characteristics (T
= 25 OC unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -25 V
Breakdown Voltage Temp. Coefficient ID = -250 µA, Referenced to 25oC -22 mV / oC
/∆T
J
Zero Gate Voltage Drain Current VDS = -20 V, V
= 0 V -1 µA
GS
TJ = 55°C -10 µA
I
GSS
Gate - Body Leakage Current VGS = -8 V, V
= 0 V -100 nA
DS
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -0.65 -0.82 -1.5 V
Gate Threshold Voltage Temp.Coefficient ID = -250 µA, Referenced to 25oC 2 mV / oC
/∆T
J
Static Drain-Source On-Resistance VGS = -4.5 V, ID = -0.41 A 0.85 1.1
Ω
TJ =125°C 1.2 1.9
VGS = -2.7 V, ID = -0.25 A 1.15 1.5
I
D(ON)
g
FS
On-State Drain Current VGS = -4.5 V, VDS = -5 V -1.5 A
Forward Transconductance VDS = -5 V, ID = -0.41 A 0.9 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 10 V, VGS = 0 V,
Output Capacitance 34 pF
f = 1.0 MHz
62 pF
Reverse Transfer Capacitance 10 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = -5 V, ID = -0.5 A,
Turn - On Rise Time 8 16 ns
VGS = -4.5 V, R
GEN
= 6 Ω
7 15 ns
Turn - Off Delay Time 55 80 ns
Turn - Off Fall Time 35 60 ns
Total Gate Charge VDS = -5 V, ID = -0.41 A,
Gate-Source Charge 0.31 nC
VGS = -4.5 V
1.1 1.5 nC
Gate-Drain Charge 0.29 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
JA
θ
by design while R
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Maximum Continuous Source Current -0.25 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.25 A (Note 2) -0.85 -1.2 V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design. R
CA
θ
= 415OC/W on minimum pad mounting on FR-4 board in still air.
JA
θ
is guaranteed
JC
θ
FDG6304P Rev.E1
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