Fairchild FDG6303N service manual
FDG6303N
Dual N-Channel,
General Description Features
Digital FET
September 2001
These dual N-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
SC70-6
SOT-23
SuperSOT
S2
G2
D1
.03
D2
SC70-6
G1
S1
25 V, 0.50 A continuous, 1.5 A peak.
R
R
DS(ON)
= 0.45 Ω @ VGS= 4.5 V,
DS(ON)
=0.60 Ω @ VGS= 2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (V
GS(th)
< 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
TM
-6
SuperSOT
TM
-8
1 or 4
2 or 5
3 or 6
SO-8
*
6 or 3
5 or 2
4 or 1
SOT-223
*
* The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter FDG6303N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 25 V
Gate-Source Voltage V
- 0.5 to +8
Drain/Output Current - Continuous 0.5 A
- Pulsed 1.5
P
D
T
J,TSTG
ESD Electrostatic Discharge Rating MIL-STD-883D
Maximum Power Dissipation (Note 1) 0.3 W
Operating and Storage Temperature Range -55 to 150 °C
6.0 kV
Human Body Model (100 pF / 1500
Ω)
THERMAL CHARACTERISTICS
R
JA
θ
Thermal Resistance, Junction-to-Ambient 415 °C/W
FDG6303N Rev.F
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
I
GSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 25 V
Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25oC 26 mV/oC
/∆T
J
Zero Gate Voltage Drain Current VDS = 20 V, V
Gate - Body Leakage Current VGS = 8 V, V
= 0 V 1 µA
GS
T
= 55°C 10 µA
J
= 0 V 100 nA
DS
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.65 0.8 1.5 V
Gate Threshold Voltage Temp.Coefficient ID = 250 µA, Referenced to 25oC -2.6 mV/oC
/∆T
J
Static Drain-Source On-Resistance VGS = 4.5 V, ID = 0.5 A 0.34 0.45
Ω
TJ =125°C 0.55 0.77
= 2.7 V, ID = 0.2 A 0.44 0.6
V
GS
I
g
D(ON)
FS
On-State Drain Current VGS = 2.7 V, VDS = 5 V 0.5 A
Forward Transconductance VDS = 5 V, ID = 0.5 A 1.45 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = 10 V, VGS = 0 V,
Output Capacitance 28 pF
f = 1.0 MHz
50 pF
Reverse Transfer Capacitance 9 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 5 V, ID = 0.5 A,
V
= 4.5 V, R
Turn - On Rise Time 8.5 18 ns
GS
GEN
= 50 Ω
3 6 ns
Turn - Off Delay Time 17 30 ns
Turn - Off Fall Time 13 25 ns
Total Gate Charge VDS = 5 V, ID = 0.5 A,
V
= 4.5 V
Gate-Source Charge 0.38 nC
GS
1.64 2.3 nC
Gate-Drain Charge 0.45 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
JA
θ
by design while R
2. Pulse Test: Pulse Width <
Maximum Continuous Source Current 0.25 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.25 A (Note 2) 0.8 1.2 V
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design. R
CA
θ
300µs, Duty Cycle < 2.0%.
= 415OC/W on minimum pad mounting on FR-4 board in still air.
JA
θ
is guaranteed
JC
θ
FDG6303N Rev.F
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