Fairchild FDD86102LZ service manual

FDD86102LZ

G

S

D

TO-252

D-PAK

(TO-252)

D

S

G

N-Channel PowerTrench® MOSFET

100 V, 35 A, 22.5 mΩ

FDD86102LZ N-Channel PowerTrench

October 2010

Features

 Max r

 Max r

 HBM ESD protection level > 6 kV typical (Note 4)

 Very low Qg and Qgd compared to competing trench

technologies

 Fast switching speed

 100% UIL tested

 RoHS Compliant

= 22.5 mΩ at VGS = 10 V, ID = 8 A

DS(on)

= 31 mΩ at VGS = 4.5 V, ID = 7 A

DS(on)

General Description

This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench
been especially tailored to minimize the on-state resistance and
switching loss. G-S zener has been added to enhance ESD
voltage level.

®

process that has

Applications

 DC - DC Conversion

 Inverter

 Synchronous Rectifier

®

MOSFET

MOSFET Maximum Ratings T

Symbol Parameter Ratings Units

V

DS

V

GS

I

D

E

AS

P

D

, T

T

J

STG

Drain to Source Voltage 100 V

Gate to Source Voltage ±20 V

Drain Current -Continuous (Package limited) TC = 25 °C 42

-Continuous (Silicon limited) T

-Continuous T

-Pulsed 40

Single Pulse Avalanche Energy (Note 3) 84 mJ

Power Dissipation TC = 25 °C 54

Power Dissipation T

Operating and Storage Junction Temperature Range -55 to +150 °C

= 25 °C unless otherwise noted

C

= 25 °C 35

C

= 25 °C (Note 1a) 8

A

= 25 °C (Note 1a) 3.1

A

A

W

Thermal Characteristics

R

θJC

R

θJA

Thermal Resistance, Junction to Case 2.3

Thermal Resistance, Junction to Ambient (Note 1a ) 40

°C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity

FDD86102LZ FDD86102LZ D-PAK(TO-252) 13 ’’ 12 mm 2500 units

©2010 Fairchild Semiconductor Corporation
FDD86102LZ Rev.C

1

www.fairchildsemi.com

FDD86102LZ N-Channel PowerTrench

Electrical Characteristics T

= 25 °C unless otherwise noted

J

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics

BV

DSS

ΔBV

DSS

ΔT

J

I

DSS

I

GSS

On Characteristics

V

GS(th)

ΔV

GS(th)

ΔT

J

r

DS(on)

g

FS

Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 100 V

Breakdown Voltage Temperature
Coefficient

Zero Gate Voltage Drain Current VDS = 80 V, V

Gate to Source Leakage Current VGS = ±20 V, V

(Note 2)

I

= 250 μA, referenced to 25 °C 69 mV/°C

D

= 0 V 1 μA

GS

= 0 V ±10 μA

DS

Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 1.0 1.5 3.0 V

Gate to Source Threshold Voltage
Temperature Coefficient

Static Drain to Source On Resistance

I

= 250 μA, referenced to 25 °C -6 mV/°C

D

V

= 10 V, ID = 8 A 17.8 22.5

GS

= 4.5 V, ID = 7 A 23.2 31

GS

V

= 10 V, ID = 8 A, TJ = 125 °C 31.1 40

GS

Forward Transconductance VDS = 5 V, ID = 8 A 31 S

Dynamic Characteristics

C

iss

C

oss

C

rss

R

g

Input Capacitance

Output Capacitance 181 245 pF

Reverse Transfer Capacitance 7.7 15 pF

Gate Resistance 0.6 Ω

Switching Characteristics

t

d(on)

t

r

t

d(off)

t

f

Q

Q

Q

Q

g

g

gs

gd

Turn-On Delay Time

Rise Time 2.3 10 ns

Turn-Off Delay Time 20 32 ns

Fall Time 2.3 10 ns

Total Gate Charge VGS = 0 V to 10 V

Total Gate Charge VGS = 0 V to 4.5 V 8.7 13 nC

Gate to Source Gate Charge 2.7 nC

Gate to Drain “Miller” Charge 2.4 nC

= 50 V, VGS = 0 V,

V

DS

f = 1 MHz

= 50 V, ID = 8 A,

V

DD

V

= 10 V, R

GS

GEN

= 6 Ω

V

DD

I

= 8 A

D

= 50 V,

1157 1540 pF

6.6 14 ns

18 26 nC

mΩV

®

MOSFET

Drain-Source Diode Characteristics

V

= 0 V, IS = 8 A (Note 2) 0.82 1.3

V

SD

t

rr

Q

rr

Notes:

is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.

1. R

θJA

R

θJC

Source to Drain Diode Forward Voltage

Reverse Recovery Time

Reverse Recovery Charge 43 70 nC

is guaranteed by design while R

is determined by the user’s board design.

θJA

a. 40 °C/W when mounted on a
1 in2 pad of 2 oz copper.

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.

3. Starting TJ = 25°C, L = 1 mH, IAS = 13 A, VDD = 90 V, VGS = 10 V.

4. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.

©2010 Fairchild Semiconductor Corporation
FDD86102LZ Rev.C

GS

= 0 V, IS = 2.6 A (Note 2) 0.75 1.2

V

GS

= 8 A, di/dt = 100 A/μs

I

F

2

43 70 ns

b. 96 °C/W when mounted on a
minimum pad of 2 oz copper.

www.fairchildsemi.com

V