Fairchild FDD6796A, FDU6796A-F071 service manual
March 2009
FDD6796A / FDU6796A_F071
N-Channel PowerTrench® MOSFET
25 V, 5.7 mΩ
Features
Max r
Max r
100% UIL tested
RoHS Compliant
= 5.7 mΩ at VGS = 10 V, ID = 20 A
DS(on)
= 15.0 mΩ at VGS = 4.5 V, ID = 15.2 A
DS(on)
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency of DC/DC converters using either
synchronous or conventional switching PWM controllers. It has
been optimized for low gate charge, low r
switching speed.
DS(on)
and fast
Applications
Vcore DC-DC for Desktop Computers and Servers
VRM for Intermediate Bus Architecture
D
FDD6796A / FDU679A_F071 N-Channel PowerTrench
G
S
D-PAK
(TO-252)
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
E
AS
P
D
, T
T
J
STG
Drain to Source Voltage 25 V
Gate to Source Voltage ±20 V
Drain Current -Continuous (Package limited) TC = 25 °C 40
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 150
Single Pulse Avalanche Energy (Note 3) 40 mJ
Power Dissipation TC = 25 °C 42
Power Dissipation T
Operating and Storage Junction Temperature Range -55 to +175 °C
D
G
D
S
Short-Lead I-PAK
(TO-251AA)
= 25 °C unless otherwise noted
C
= 25 °C 67
C
= 25 °C (Note 1a) 20
A
= 25 °C (Note 1a) 3.7
A
G
S
Thermal Characteristics
R
θJC
R
θJA
Thermal Resistance, Junction to Case 3.6
Thermal Resistance, Junction to Ambient (Note 1a) 40
Package Marking and Ordering Information
®
MOSFET
A
W
°C/W
Device Marking Device Package Reel Size Tape Width Quantity
FDD6796A FDD6796A D-PAK (TO-252) 13 ’’ 12 mm 2500 units
FDU6796A FDU6796A_F071 TO-251AA N/A(Tube) N/A 75 units
©2009 Fairchild Semiconductor Corporation
FDD6796A / FDU6796A_F071 Rev.C1
1
www.fairchildsemi.com
FDD6796A / FDU679A_F071 N-Channel PowerTrench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
∆BV
∆T
I
DSS
I
GSS
DSS
DSS
J
Drain to Source Breakdown Voltage ID = 250 µA, VGS = 0 V 25 V
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current VDS = 20 V, V
Gate to Source Leakage Current VGS = ±20 V, V
I
= 250 µA, referenced to 25 °C 16 mV/°C
D
= 0 V 1 µA
GS
= 0 V ±100 nA
DS
On Characteristics
V
GS(th)
∆V
∆T
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage VGS = VDS, ID = 250 µA 1.0 1.9 3.0 V
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
I
= 250 µA, referenced to 25 °C -6 mV/°C
D
V
= 10 V, ID = 20 A 4.3 5.7
GS
= 4.5 V, ID = 15.2 A 11.1 15.0
GS
= 10 V, ID = 20 A, TJ = 150 °C 6.5 8.6
V
GS
Forward Transconductance VDS = 5 V, ID = 20 A 118 S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance 298 400 pF
Reverse Transfer Capacitance 266 400 pF
Gate Resistance 1.2 Ω
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
Q
g
g
gs
gd
Turn-On Delay Time
Rise Time 714ns
Turn-Off Delay Time 19 34 ns
Fall Time 410ns
Total Gate Charge VGS = 0 V to 10 V
Total Gate Charge VGS = 0 V to 5 V 14 20 nC
Gate to Source Charge 4.0 nC
Gate to Drain “Miller” Charge 5.7 nC
= 13 V, VGS = 0 V,
V
DS
f = 1 MHz
= 13 V, ID = 20 A,
V
DD
V
= 10 V, R
GS
GEN
= 6 Ω
V
DD
I
= 20 A
D
= 13 V,
1336 1780 pF
816ns
24 34 nC
mΩV
®
MOSFET
Drain-Source Diode Characteristics
V
SD
t
rr
Q
rr
Notes:
1: R
θJA
R
θJC
2: Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%.
of 40 mJ is based on starting TJ = 25 °C, L = 1 mH, IAS = 9 A, VDD = 23 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 21 A.
3: E
AS
©2009 Fairchild Semiconductor Corporation
FDD6796A / FDU6796A_F071 Rev.C1
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge 4 10 nC
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins .
is guaranteed by design while R
is determined by the user’s board design.
θJA
a)
40 °C/W when mounted on a
1 in2 pad of 2 oz copper
V
= 0 V, IS = 3.1 A (Note 2) 0.8 1.2
GS
= 0 V, IS = 20 A (Note 2) 0.9 1.3
V
GS
= 20 A, di/dt = 100 A/µs
I
F
2
b)
15 27 ns
96 °C/W when mounted on
a minimum pad
V
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