Fairchild FDD6760A service manual

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FDD6760A
N-Channel PowerTrench® MOSFET
25 V, 3.2 m Features
Max rMax r100% UIL testRoHS Compliant
= 3.2 mΩ at VGS = 10 V, ID = 27 A
DS(on)
= 6.0 mΩ at VGS = 4.5 V, ID = 21 A
DS(on)
General Description
This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low r switching speed.
Applications
Vcore DC-DC for Desktop Computers and ServersVRM for Intermediate Bus Architecture
January 2009
and fast
DS(on)
FDD6760A N-Channel Power Trench
®
MOSFET
D
D
G
S
D-PAK
TO-252
G
TO-252
S
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
E
AS
P
D
, T
T
J
STG
Thermal Characteristics
Drain to Source Voltage 25 V Gate to Source Voltage ±20 V Drain Current -Continuous (Package limited) TC = 25 °C 50
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 200 Single Pulse Avalanche Energy (Note 3) 72 mJ Power Dissipation TC = 25 °C 65 Power Dissipation T Operating and Storage Junction Temperature Range -55 to +175 °C
= 25 °C unless otherwise noted
C
= 25 °C 131
C
= 25 °C (Note 1a) 27
A
= 25 °C (Note 1a) 3.7
A
A
W
R
θJC
R
θJA
Thermal Resistance, Junction to Case 2.3 Thermal Resistance, Junction to Ambient (Note 1a) 40
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDD6760A FDD6760A D-PAK (TO-252) 13 ’’ 12 mm 2500 units
©2009 Fairchild Semiconductor Corporation FDD6760A Rev.C
°C/W
1
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FDD6760A N-Channel Power Trench
Electrical Characteristics T
= 25 °C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
BVT
I
DSS
I
GSS
DSS
Drain to Source Breakdown Voltage ID = 250 µA, VGS = 0 V 25 V Breakdown Voltage Temperature
DSS
Coefficient
J
Zero Gate Voltage Drain Current VDS = 20 V, V Gate to Source Leakage Current VGS = ±20 V, V
I
= 250 µA, referenced to 25 °C 16 mV/°C
D
= 0 V 1 µA
GS
= 0 V ±100 nA
DS
On Characteristics
V
GS(th)
VT
r
DS(on)
g
FS
GS(th)
Gate to Source Threshold Voltage VGS = VDS, ID = 250 µA 1.0 1.6 3.0 V Gate to Source Threshold Voltage
Temperature Coefficient
J
Static Drain to Source On Resistance
I
= 250 µA, referenced to 25 °C -7 mV/°C
D
V
= 10 V, ID = 27 A 2.3 3.2
GS
= 4.5 V, ID = 21 A 4.4 6.0
GS
= 10 V, ID = 27 A, TJ = 150 °C 3.5 4.9
V
GS
Forward Transconductance VDS = 5 V, ID = 27 A 186 S
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance Output Capacitance 525 700 pF Reverse Transfer Capacitance 470 710 pF Gate Resistance f = 1MHz 1.3
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q Q
g g gs gd
Turn-On Delay Time Rise Time 918ns Turn-Off Delay Time 28 ns Fall Time 6ns Total Gate Charge VGS = 0 V to 10 V Total Gate Charge VGS = 0 V to 5 V 25 35 nC Gate to Source Charge 6 nC Gate to Drain “Miller” Charge 9.9 nC
= 13 V, VGS = 0 V,
V
DS
f = 1MHz
= 13 V, ID = 27 A,
V
DD
V
= 10 V, R
GS
GEN
= 6
V
DD
I
= 17 A
D
= 13 V,
2380 3170 pF
10 20 ns
44 62 nC
mV
®
MOSFET
Drain-Source Diode Characteristics
V
= 0 V, IS = 3.1 A (Note 2) 0.7 1.2
V
SD
t
rr
Q
rr
Notes: 1: R
θJA
R
θJC
2: Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%. 3: EAS of 72 mJ is based on starting TJ = 25 °C, L = 1 mH, IAS = 12 A, VDD = 23 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 29 A.
©2009 Fairchild Semiconductor Corporation FDD6760A Rev.C
Source to Drain Diode Forward Voltage Reverse Recovery Time
Reverse Recovery Charge 8 16 nC
is the sum of the juncti on-t o- cas e a nd cas e-t o -am bi en t th e rma l res ist an ce whe re the ca s e th er ma l ref ere nc e i s de f ine d as the s older mounting surface of the drain pins.
is guaranteed by design while R
is determined by the user’s board design.
θJA
a)
40 °C/W when mounted on a 1 in2 pad of 2 oz copper
GS
= 0 V, IS = 27 A (Note 2) 0.8 1.3
V
GS
= 27A, di/dt = 100 A/µs
I
F
2
21 34 ns
b)
96 °C/W when mounted on a minimum pad.
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V
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