Fairchild FDD5353 service manual

tm
FDD5353
(
)
N-Channel Power Trench® MOSFET
60V, 50A, 12.3m
Features
Max rMax r100% UIL TestedRoHS Compliant
= 12.3mΩ at VGS = 10V, ID = 10.7A
DS(on)
= 15.4mΩ at VGS = 4.5V, ID = 9.5A
DS(on)
General Description
This N-Channel MOSFET is produced using Fairchild Semiconductor‘s advanced Power Trench been especially tailored to minimize the on-state resistance and yet maintain superior switching performance.
Application
InverterSynchronous rectifierPrimary switch
FDD5353 N-Channel Power Trench
March 2008
®
process that has
MOSFET
D
G
D
S
D-PAK
TO-252
G
TO-252
S
MOSFET Maximum Ratings T
Symbol Parameter Ratings Units
V
DS
V
GS
I
D
E
AS
P
D
, T
T
J
STG
Thermal Characteristics
R
θJC
R
θJA
Package Marking and Ordering Information
Drain to Source Voltage 60 V Gate to Source Voltage ±20 V Drain Current -Continuous (Package limited) TC = 25°C 50
-Continuous (Silicon limited) T
-Continuous T
-Pulsed 100 Single Pulse Avalanche Energy (Note 3) 253 mJ Power Dissipation TC = 25°C 69 Power Dissipation T Operating and Storage Junction Temperature Range -55 to +150 °C
Thermal Resistance, Junction to Case 1.8 Thermal Resistance, Junction to Ambient (Note 1a) 40
= 25°C unless otherwise noted
C
= 25°C 54
C
= 25°C (Note 1a) 11.5
A
= 25°C (Note 1a) 3.1
A
A
W
°C/W
Device Marking Device Package Reel Size Tape Width Quantity
FDD5353 FDD5353 D-PAK (TO-252) 13’’ 12mm 2500 units
©2008 Fairchild Semiconductor Corporation FDD5353 Rev.C
1
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FDD5353 N-Channel Power Trench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
BV
DSS
T
J
I
DSS
I
GSS
On Characteristics
V
GS(th)
V
GS(th)
T
J
r
DS(on)
g
FS
Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 60 V Breakdown Voltage Temperature
Coefficient Zero Gate Voltage Drain Current V Gate to Source Leakage Current VGS = ±20V, V
ID = 250µA, referenced to 25°C 77 mV/°C
= 0V, VDS = 48V, 1 µA
GS
= 0V ±100 nA
DS
Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.0 1.8 3.0 V Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance VDD = 5V, ID = 10.7A 41 S
ID = 250µA, referenced to 25°C -8 mV/°C VGS = 10V, ID = 10.7A 10.1 12.3
VGS = 10V , ID = 10.7A, TJ = 125°C 16.7 20.3
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance Output Capacitance 215 285 pF Reverse Transfer Capacitance 120 180 pF
VDS = 30V, VGS = 0V, f = 1MHz
2420 3215 pF
Gate Resistance f = 1MHz 1.7
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q Q Q Q
g g gs gd
Turn-On Delay Time Rise Time 6 11 ns Turn-Off Delay Time 36 58 ns
VDD = 30V, ID = 10.7A, VGS = 10V, R
GEN
= 6
11 20 ns
Fall Time 4 10 ns Total Gate Charge VGS = 0V to 10V Total Gate Charge VGS = 0V to 4.5V 23 32 nC Gate to Source Charge 7 nC
VDD = 30V, ID = 10.7A
46 65 nC
Gate to Drain “Miller” Charge 9 nC
mVGS = 4.5V, ID = 9.5A 12.1 15.4
MOSFET
Drain-Source Diode Characteristics
V
SD
t
rr
Q
rr
Notes: 1: R
θJA
R
θJC
2: Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%. 3: Starting T
©2008 Fairchild Semiconductor Corporation FDD5353 Rev.C
Source to Drain Diode Forward Voltage Reverse Recovery Time
Reverse Recovery Charge 21 34 nC
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.
is guaranteed by design while R
= 25°C, L = 3mH, IAS = 13A, VDD = 60V, VGS = 10V.
J
is determined by the user’s board design.
θJA
V V
IF = 10.7A, di/dt = 100A/µs
a)
40°C/W when mounted on a
2
pad of 2 oz copper
1 in
= 0V, IS = 10.7A (Note 2) 0.8 1.3
GS
= 0V, IS = 2.6A (Note 2) 0.7 1.2
GS
28 45 ns
b)
96°C/W when mounted on a minimum pad.
2
V
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FDD5353 N-Channel Power Trench
Typical Characteristics T
100
VGS = 10V
80
60
40
, DRAIN CURRENT (A)
20
D
I
0
012345
V
Figure 1.
2.0
ID = 10.7A
1.8
= 10V
V
GS
1.6
1.4
1.2
1.0
NORMALIZED
0.8
0.6
DRAIN TO SOURCE ON-RESISTANCE
0.4
-75 -50 -25 0 25 50 75 100 125 150
T
Figu r e 3. Nor m a lized O n - R esist a n c e
vs Junction Temperature
VGS = 4.5V
VGS = 4V
PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX
, DRAIN TO SOURCE VOLTAGE (V)
DS
On-Region Characteristics Figure 2.
, JUNCTION TEMPERATURE (
J
= 25°C unless otherwise noted
J
VGS = 3.5V
VGS = 3V
o
C)
3.0
2.5
VGS = 3V
VGS = 3.5V
VGS = 4V
2.0
V
= 4.5V
1.5
NORMALIZED
1.0
PULSE DURATION = 80µs
DRAIN TO SOURCE ON-RESISTANCE
0.5 020406080100
DUTY CYCLE = 0.5%MAX
I
, DRAIN CURRENT(A)
D
GS
V
GS
Norma l i z e d O n - Resistance
vs Drain Current and Gate Voltage
40
32
(m)
24
DRAIN TO
,
16
DS(on)
r
8
SOURCE ON-RESISTANCE
0
2345678910
V
GS
Figure 4.
On-Resista nce vs Gate to
PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX
ID = 10.7A
TJ = 125oC
TJ = 25oC
, GATE TO SOURCE VOLTAGE (V)
Source Voltage
= 10V
MOSFET
100
PULSE DURATION = 80µs DUTY CYCLE = 0.5%MAX
80
V
= 5V
DS
60
40
, DRAIN CURRENT (A)
20
D
I
0
12345
TJ = 150oC
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
©2008 Fairchild Semiconductor Corporation FDD5353 Rev.C
TJ = -55oC
TJ = 25oC
200
100
V
= 0V
GS
10
TJ = 150oC
1
TJ = 25oC
0.1
0.01
, REVERSE DRAIN CURRENT (A)
S
I
0.001
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6.
Source to Dr ai n Diode
TJ = -55oC
Forward Voltage vs Source Current
3
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FDD5353 N-Channel Power Trench
Typical Characteristics T
10
ID = 10.7A
8
6
4
2
, GATE TO SOURCE VOLTAGE(V)
GS
V
0
0 1020304050
Figure 7.
Qg, GATE CHARGE(nC)
Gate Charge Characteristics Figure 8.
20
10
, AVALANCHE CURRENT(A)
AS
I
1
0.01 0.1 1 10 100
tAV, TIME IN AVALANCHE(ms)
Figure 9.
Uncl a m p e d I n duct i v e
Switching Capability
V
DD
VDD = 40V
TJ = 125oC
= 25°C unless otherwise noted
J
= 20V
VDD = 30V
TJ = 25oC
10000
1000
100
CAPACITANCE (pF)
f = 1MHz V
= 0V
GS
10
0.1 1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Capacitance vs Drain
to Source Voltage
60
50
V
= 10V
GS
40
Limited by Package
30
V
= 4.5V
GS
, DRAIN CURRENT (A)
I
20
D
R
= 1.8oC/W
θJC
10
0
25 50 75 100 125 150
T
, CASE TEMPERATURE (
C
Figure 10.
Ma xim um C ont inu ous Drain
o
C)
Current vs Case Temperature
C
iss
C
oss
C
rss
30
MOSFET
200
100
10
, DRAIN CURRENT (A)
D
I
0.1
THIS AREA IS LIMITED BY r
1
DS(on)
SINGLE PULSE T
= MAX RATED
J
R
θJC
= 25
T
C
0.1 1 10 100
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
©2008 Fairchild Semiconductor Corporation FDD5353 Rev.C
= 1.8
5
10
100us
4
1ms
10ms 100ms
o
C/W
o
C
DC
200
10
3
10
2
10
), PEAK TRANSIENT POWER (W)
PK
P(
10
10
VGS = 10V
-6
-5
10
Figure 12.
SINGLE PULSE
o
R
= 1.8
C/W
θJC
o
= 25
C
T
C
-4
-3
-2
-1
10
t, PULSE WIDTH (sec)
10
10
10
1
Single Pulse Maximum
Power Dissipation
4
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FDD5353 N-Channel Power Trench
Typical Characteristics T
2
NORMALIZED THERMAL
NORMALIZED THERMAL
θJC
Z
0.01
IMPEDANCE,
0.001
5E-4
θJA
Z
0.01
IMPEDANCE,
0.001
0.0001
1
0.1
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
-6
10
10
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
-4
10
-3
10
SINGLE PULSE R
θJC
-5
= 25°C unless otherwise noted
J
NOTES:
= 1.8oC/W
-4
10
-3
10
DUTY FACTOR: D = t PEAK TJ = PDM x Z
-2
10
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Transient Thermal Response Curve
SINGLE PULSE R
= 96oC/W
θJA
(Note 1b)
-2
10
-1
10
110
t, RECTANGULAR PULSE DURATION (sec)
NOTES: DUTY FACTOR: D = t
PEAK TJ = PDM x Z
P
DM
t
1
t
2
1/t2
x R
+ T
θJc
θJc
C
-1
10
P
DM
t
1
t
2
1/t2
x R
+ T
θJA
θJA
A
100 1000
1
MOSFET
©2008 Fairchild Semiconductor Corporation FDD5353 Rev.C
Figure 14.
Transient Thermal Response Curve
5
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®
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tm
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks.
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®
®
are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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FDD5353 N-Channel Power Trench
MOSFET
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NO TICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE U NDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND TH E TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided
2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
in the labeling, can be reasonably expected to result in a significant injury of the user.
PRODUCT STATUS DEFINITIONS Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In Design
This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.
This datasheet contains preliminary data; supplementary data will be pub-
Preliminary First Production
lished at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.
No Identification Needed Full Production
Obsolete Not In Production
©2008 Fairchild Semiconductor Corporation FDD5353 Rev.C
This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.
This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.
Rev. I34
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