Fairchild FDD3510H service manual
FDD3510H
Dual N & P-Channel PowerTrench® MOSFET
N-Channel: 80V, 13.9A, 80mΩ P-Channel: -80V, -9.4A, 190mΩ
FDD3510H Dual N & P-Channel PowerTrench
April 2008
Features
Q1: N-Channel
Max r
Max r
Q2: P-Channel
Max r
Max r
100% UIL Tested
RoHS Compliant
= 80mΩ at VGS = 10V, ID = 4.3A
DS(on)
= 88mΩ at VGS = 6V, ID = 4.1A
DS(on)
= 190mΩ at VGS = -10V, ID = -2.8A
DS(on)
= 224mΩ at VGS = -4.5V, ID = -2.6A
DS(on)
D1/D2
S1
Dual DPAK 4L
G1
S2
G2
General Description
These dual N and P-Channel enhancement mode Power
MOSFETs are produced using Fairchild Semiconductor’s
advanced PowerTrench
tailored to minimize on-state resistance and yet maintain
superior switching performance.
®
process that has been especially
Applications
Inverter
H-Bridge
G1
D1 D2
S1
N-Channel
G2
S2
P-Channel
®
MOSFET
MOSFET Maximum Ratings T
Symbol Parameter Q1 Q2 Units
V
DS
V
GS
I
D
P
D
E
AS
, T
T
J
STG
Thermal Characteristics
R
θJC
R
θJC
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDD3510H FDD3510H TO-252-4L 13” 12mm 2500 units
©2008 Fairchild Semiconductor Corporation
FDD3510H Rev.C
Drain to Source Voltage 80 -80 V
Gate to Source Voltage ±20 ±20 V
Drain Current - Continuous TC = 25°C 13.9 -9.4
- Pulsed 20 -10
Power Dissipation for Single Operation TC = 25°C (Note 1) 35 32
T
Single Pulse Avalanche Energy (Note 3) 37 54 mJ
Operating and Storage Junction Temperature Range -55 to +150 °C
Thermal Resistance, Junction to Case, Single Operation for Q1 (Note 1) 3.5
Thermal Resistance, Junction to Case, Single Operation for Q2 (Note 1) 3.9
= 25°C unless otherwise noted
C
1
= 25°C 4.3 -2.8
A
= 25°C (Note 1a) 3.1
A
= 25°C (Note 1b) 1.3
A
A - Continuous T
W T
°C/W
www.fairchildsemi.com
FDD3510H Dual N & P-Channel PowerTrench
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Off Characteristics
BV
∆BV
∆T
I
DSS
I
GSS
DSS
DSS
J
=250µA, VGS = 0V
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
D
I
= -250µA, VGS = 0V
D
ID = 250µA, referenced to 25°C
I
= -250µA, referenced to 25°CQ1Q2
D
V
= 64V, V
DS
V
= -64V, V
DS
Gate to Source Leakage Current VGS = ±20V, V
GS
GS
DS
= 0V
= 0V
= 0V
Q1Q280
-80
Q1
Q2
Q1
Q2
V
84
-67
1
-1
±100
±100nAnA
mV/°C
I
On Characteristics
V
V
GS(th)
∆V
∆T
r
DS(on)
g
FS
GS(th)
J
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance
= VDS, ID = 250µA
GS
V
= VDS, ID = -250µA
GS
ID = 250µA, referenced to 25°C
I
= -250µA, referenced to 25°C
D
= 10V, ID = 4.3A
V
GS
V
= 6.0V, ID = 4.1A
GS
V
= 10V, ID = 4.3A, TJ = 125°C
GS
V
= -10V, ID = -2.8A
GS
V
= -4.5V, ID = -2.6A
GS
V
= -10V, ID = -2.8A, TJ = 125°C
GS
V
= 10V, ID = 4.3A
DD
V
= -5V, ID = -2.8A
DD
Q1Q22.0
-1.0
Q1
Q2
Q1
Q2
Q1
Q2
2.6
-1.6
-6.7
4.6
64
70
121
153
184
259
15
6.8
4.0
-3.0
mV/°C
80
88
152
190
224
322
µA
V
mΩ
S
®
MOSFET
Dynamic Characteristics
C
iss
C
oss
C
rss
R
g
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance f = 1MHz
Switching Characteristics
t
d(on)
t
r
t
d(off)
t
f
Q
Q
Q
g(TOT)
gs
gd
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
Q1
= 40V, VGS = 0V, f = 1MHZ
V
DS
Q2
= -40V, VGS = 0V, f = 1MHZ
V
DS
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
600
660
56
50
27
25
1.7
7.2
800
880
75
70
41
40
pF
pF
pF
Ω
7
Q1
V
= 40V, ID = 4.3A,
DD
V
= 10V, R
GS
GEN
= 6Ω
Q2
= -40V, ID = -2.8A,
V
DD
V
= -10V, R
GS
GEN
= 6Ω
Q1
V
= 10V, VDD = 40V, ID = 4.3A
GS
Q2
= -10V, VDD = -40V, ID = -2.8A
V
GS
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
Q1
Q2
16
25
13
14
2.3
1.9
3.2
2.9
13
6
11
2
10
3
10
29
40
2
10
5
10
18
20
ns
ns
ns
ns
nC
nC
nC
FDD3510H Rev.C
2
www.fairchildsemi.com
Electrical Characteristics T
= 25°C unless otherwise noted
J
Symbol Parameter Test Conditions Type Min Typ Max Units
Drain-Source Diode Characteristics
0.8
-0.8
293046
283045
1.2
-1.2
48
48
is determined
θCA
V
= 0V, IS = 2.6A (Note 2)
V
SD
t
rr
Q
rr
Notes:
1. R
is determined with the device mo unted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
θJA
by the user's board design.
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
GS
V
= 0V, IS = -2.6A (Note 2)Q1Q2
GS
Q1
I
= 4.3A, di/dt = 100A/s
F
Q2
I
= -2.8A, di/dt = 100A/s
F
Q1
Q2
Q1
Q2
is guaranteed by design while R
θJC
FDD3510H Dual N & P-Channel PowerTrench
V
ns
nC
Q1
Q2
2. Pulse Test: Pulse Width < 300µs, Duty cycle < 2.0%.
3. Starting TJ = 25°C, N-ch: L = 3mH, IAS = 5A, VDD = 80V, VGS = 10V; P-ch: L = 3mH, IAS = -6A, VDD = -80V, VGS = -10V.
a. 40°C/W when mounted on
2
a 1 in
pad of 2 oz copper
Scale 1 : 1 on letter size paper
a. 40°C/W when mounted on
2
a 1 in
pad of 2 oz copper
Scale 1 : 1 on letter size paper
b. 96°C/W when mounted on a
minimum pad of 2 oz copper
b. 96°C/W when mounted on a
minimum pad of 2 oz copper
®
MOSFET
FDD3510H Rev.C
3
www.fairchildsemi.com
Loading...