FDC658P
Single P-Channel, Logic Level, PowerTrenchTM MOSFET
General Description Features
February 1999
This P-Channel Logic Level MOSFET is produced
using Fairchild Semiconductor's advanced
PowerTrench process that has been especially tailored
to minimize the on-state resistance and yet maintain
low gate charge for superior switching performance.
These devices are well suited for notebook computer
applications: load switching and power management,
battery charging circuits, and DC/DC conversion.
SOT-23
SuperSOTTM-8
S
D
D
.658
G
D
1
pin
SuperSOT -6
TM
D
-4 A, -30 V. R
R
= 0.050 Ω @ VGS = -10 V
DS(ON)
= 0.075 Ω @ VGS = -4.5 V.
DS(ON)
Low gate charge (8nC typical).
High performance trench technology for extremely low
R
.
DS(ON)
SuperSOTTM-6 package: small footprint (72% smaller than
standard SO-8); low profile (1mm thick).
SO-8
SOT-223SuperSOTTM-6
1
2
3
3
SOIC-16
6
5
4
Absolute Maximum Ratings T
Symbol Parameter Ratings Units
V
V
I
D
Drain-Source Voltage -30 V
DSS
Gate-Source Voltage - Continuous ±20 V
GSS
Drain Current - Continuous (Note 1a) -4 A
= 25°C unless otherwise note
A
- Pulsed -20
P
TJ,T
THERMAL CHARACTERISTICS
R
R
© 1999 Fairchild Semiconductor Corporation
Maximum Power Dissipation (Note 1a) 1.6 W
D
θ
θJC
STG
JA
(Note 1b)
0.8
Operating and Storage Temperature Range -55 to 150 °C
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W
FDC658P Rev.C
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -30 V
Breakdown Voltage Temp. Coefficient ID = -250 µA, Referenced to 25 oC -22 mV/oC
/∆T
J
Zero Gate Voltage Drain Current VDS = -24 V, V
= 0 V -1 µA
GS
TJ = 55 oC -10 µA
I
GSSF
I
GSSR
Gate - Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate - Body Leakage, Reverse VGS = -20 V, V
= 0 V -100 nA
DS
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage VDS = VGS, ID = -250 µA -1 -1.7 -3 V
Gate Threshold VoltageTemp.Coefficient ID = -250 µA, Referenced to 25 oC 4.1 mV/oC
/∆T
J
Static Drain-Source On-Resistance VGS = -10 V, ID = -4.0 A 0.041 0.05
TJ = 125 oC 0.058 0.08
VGS = -4.5 V, ID = -3.4 A 0.06 0.075
I
g
D(on)
FS
On-State Drain Current VGS = -10 V, VDS = -5 V -20 A
Forward Transconductance VDS = -5V, ID = -4 A 9 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = -15 V, VGS = 0 V, 750 pF
Output Capacitance f = 1.0 MHz 220 pF
Reverse Transfer Capacitance 100 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = -15 V, ID = -1 A, 12 22 ns
Turn - On Rise Time
VGS = -10 V, R
GEN
= 6 Ω
Turn - Off Delay Time 24 38 ns
Turn - Off Fall Time 16 27 ns
Total Gate Charge VDS = -15 V, ID = -4.0 A, 8 12 nC
Gate-Source Charge VGS = -5 V 1.8 nC
Gate-Drain Charge 3 nC
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
V
SD
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
by design while R
a. 78oC/W when mounted on a 1 in
b. 156oC/W when mounted on a minimum pad of 2oz Cu on FR-4 board.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
Continuous Source Diode Current -1.3 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = -1.3 A (Note 2) -0.76 -1.2 V
is determined by the user's board design.
CA
θ
2
pad of 2oz Cu on FR-4 board.
14 25 ns
is guaranteed
JC
θ
Ω
FDC658P Rev.C