Fairchild FDC653N service manual
FDC653N
N-Channel Enhancement Mode Field Effect Transistor
General Description Features
This N-Channel enhancement mode power field effect
transistors is produced using Fairchild's proprietary, high cell
density, DMOS technology. This very high density process is
tailored to minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMICA cards, and other
battery powered circuits where fast switching, and low in-line
power loss are needed in a very small outline surface mount
package.
5 A, 30 V. R
R
Proprietary SuperSOTTM-6 package design using copper
lead frame for superior thermal and electrical capabilities.
High density cell design for extremely low R
Exceptional on-resistance and maximum DC current
capability.
November 1997
= 0.035 Ω @ VGS = 10 V
DS(ON)
= 0.055 Ω @ VGS = 4.5 V.
DS(ON)
DS(ON)
.
SOT-23
SuperSOTTM-6
D
SuperSOTTM-8
S
SO-8
1
SOT-223
SOIC-16
6
D
.653
2
5
G
pin
SuperSOT -6
TM
Absolute Maximum Ratings T
D
1
D
= 25°C unless otherwise note
A
Symbol Parameter FDC653N Units
V
V
I
D
Drain-Source Voltage 30 V
DSS
Gate-Source Voltage - Continuous ±20 V
GSS
Drain Current - Continuous (Note 1a) 5 A
- Pulsed 15
P
TJ,T
Maximum Power Dissipation (Note 1a) 1.6 W
D
STG
(Note 1b)
Operating and Storage Temperature Range -55 to 150 °C
THERMAL CHARACTERISTICS
R
R
Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W
θJA
Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W
θJC
3
3
4
0.8
© 1997 Fairchild Semiconductor Corporation
FDC653N Rev.C
ELECTRICAL CHARACTERISTICS (T
= 25°C unless otherwise noted)
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
I
GSSF
I
GSSR
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 30 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
ID = 250 µA, Referenced to 25 o C
VDS = 24 V, V
GS
= 0 V
31
1 µA
TJ = 55oC
Gate - Body Leakage, Forward
Gate - Body Leakage, Reverse
VGS = 20 V, VDS = 0 V
VGS = -20 V, VDS= 0 V
mV /oC
10 µA
100 nA
-100 nA
ON CHARACTERISTICS (Note 2)
V
∆V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage
Gate Threshold VoltageTemp.Coefficient
/∆T
J
Static Drain-Source On-Resistance
VDS = VGS, ID = 250 µA
ID = 250 µA, Referenced to 25 o C
VGS = 10 V, ID = 5 A
1 1.7 2 V
-4.2
mV /oC
0.027 0.035
TJ = 125oC 0.042 0.056
0.046 0.055
6.2 S
I
g
D(on)
VGS = 4.5 V, ID = 4.2 A
On-State Drain Current VGS = 10 V, VDS = 5 V 8 A
FS
Forward Transconductance
VDS = 10 V, ID= 5 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
VDS = 15 V, VGS = 0 V,
Output Capacitance f = 1.0 MHz 220 pF
Reverse Transfer Capacitance 80 pF
350 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
g
gs
gd
Turn - On Delay Time VDD = 10 V, ID = 1 A, 7.5 15 ns
Turn - On Rise Time
VGS = 4.5 V, R
GEN
= 6 Ω
12 25 ns
Turn - Off Delay Time 13 25 ns
Turn - Off Fall Time 6 15 ns
Total Gate Charge
VDS = 15 V, ID = 5 A,
12 17 nC
Gate-Source Charge VGS = 10 V 2.1 nC
Gate-Drain Charge 2.6 nC
DRAIN-SOURCE DIODE CHARACTERISTICS
I
S
V
SD
Continuous Source Diode Current 1.3 A
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 1.3 A (Note 2)
0.75 1.2 V
TJ = 125oC 0.6 1
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
JA
θ
design while R
a. 78oC/W when mounted on a minimum on a 1 in
b. 156oC/W when mounted on a minimum pad of 2oz Cu in FR-4 board.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
is determined by the user's board design.
CA
θ
2
pad of 2oz Cu in FR-4 board.
is guaranteed by
JC
θ
Ω
FDC653N Rev.C
Loading...