FDC6506P
Dual P-Channel Logic Level PowerT rench MOSFET
General Description
These P-Channel logic level MOSFET s are produced using
Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize
on-state resistance and yet maintain low gate charge for
superior switching performance.
These devices have been designed to offer exceptional
power dissipation in a very small footprint for applications
where the bigger more expensive SO-8 and TSSOP-8
packages are impractical.
Applications
• Load switch
• Battery protection
• Power management
Features
• -1.8 A, -30 V. R
R
DS(on)
DS(on)
• Low gate charge (2.3nC typical).
• Fast switching speed.
• High performance trench technology for extremely
low R
• SuperSOT
than standard SO-8); low profile (1mm thick).
.
DS(ON)
TM
-6 package: small footprint (72% smaller
= 0.170 Ω @ V
= 0.280 Ω @ V
February 1999
= -10 V
GS
= -4.5 V
GS
FDC6506P
D2
S1
4
3
D1
5
2
G2
SuperSOT -6
TM
S2
G1
Absolute Maximum Ratings
6
TA = 25°C unless otherwise noted
1
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
stg
Drain-Source Voltage -30 V
Gate-Source Voltage
Drain Current - Continuous
- Pulsed -10
Power Dissipation for Si ngl e Operati on
Operating and Storage Junction Temperature Range -55 to +150
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
20 V
±
-1.8 A
0.96 W
0.9
0.7
C
°
Thermal Characteristics
R
JA
θ
R
JC
θ
Thermal Resistance, Junct i on-to-A m bi ent
Thermal Resistance, Junct i on-to-Cas e
(Note 1a)
(Note 1)
130
60
C/W
°
C/W
°
Package Outlines and Ordering Information
Device Marking Device Reel Size Tape Width Quantity
506
.
1999 Fairchild Semiconductor Corporation
FDC6506P 7’’ 8mm 3000 units
FDC6506P Rev. C
FDC6506P
yp
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min T
Off Characteristics
BV
DSS
BV
∆
T
∆
I
DSS
I
GSSF
I
GSSR
On Characteristics
V
GS(th)
GS(th)
V
∆
T
∆
R
DS(on)
I
D(on)
g
FS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA-30 V
Breakdown Voltage Temperature
DSS
Coefficient
J
ID = -250 µA, Referenced to 25°C-20 mV/
Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V -1
Gate-Body Leakage Current, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate-Body Leakage Current, Reverse VGS = -20 V, VDS = 0 V -100 nA
(Note 2)
Gate Threshold Voltage VDS = VGS, ID = -250 µA-1-1.8-3V
Gate Threshold Voltage
Temperature Coefficient
J
Static Drain-Source
On-Resistance
ID = -250 µA, Referenced to 25°C4 mV/
VGS = -10 V, ID = -1.8 A
V
= -10 V, ID = -1.8 A @125°C
GS
V
= -4.5 V, ID = -1.4 A
GS
On-State Drain Current VGS = -10 V, VDS = - 5 V -10 A
Forward Transconductance VDS = -5 V, ID = -1.8 A 3 S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance 190 pF
Output Capacitance 70 pF
Reverse Transfer Capacitance
V
= -15 V, VGS = 0 V,
DS
f = 1.0 MHz
Max Units
0.17
0.14
0.27
0.20
0.28
0.22
30 pF
C
°
A
µ
C
°
Ω
(Note 2)
Switching Characteristics
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
g
gs
gd
Turn-On Delay Time 7 14 ns
Turn-On Rise Time 8 16 ns
Turn-Off Delay Time 14 25 ns
Turn-Off Fall Time
Total Gate Charge 2.3 3.5 nC
Gate-Source Charge 1 nC
Gate-Drain Charge
V
= -15 V, ID = -1 A,
DD
V
= -4.5 V, R
GS
V
= -5 V, ID = -1.8 A,
DS
V
= -10 V
GS
GEN
= 6
Ω
26ns
0.8 nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
1. R
θJA
of the drain pins. R
sharing the dissipated heat energy equally.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Maximum Continuous Drain-Source Di ode Forward Current -0.8 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.8 A
is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface
is guaranteed by design while R
θJC
a) 130 °C/W when
mounted on a 0.125 in
pad of 2 oz. copper.
is determined by the user's board design.Both devices are assumed to be operating and
θJA
2
b) 140 °C/W when
mounted on a 0.005 in
pad of 2 oz. copper.
(Note 2)
2
-0.8 -1.2 V
c) 180 °C/W when
mounted on a 0.0015 in
pad of 2 oz. copper.
2
FDC6506P Rev. C
T ypical Characteristics
FDC6506P
10
VGS=-10V
8
6
4
, DRAIN CURRENT (A)
D
-I
2
0
012345
-7.0V
-5.5V
-4.5V
-4.0V
-3.5V
-V
, DRAIN TO SOURCE VOLTAGE (V)
DS
-3.0V
Figure 1. On-Region Characteristics.
1.4
ID=-1.8A
VGS=-10V
1.3
1.2
1.1
1
, NORMALIZED
DS(ON)
0.9
R
0.8
DRAIN-SOURCE ON-RESISTANCE
0.7
-50 -25 0 25 50 75 100 125 150
T
, JUNCTION TEMPERATURE (oC)
J
2.5
2
VGS=-4.0V
1.5
, NORMALIZED
DS(ON)
R
DRAIN-SOURCE ON-RESISTANCE
0.5
-4.5V
-5.0V
-6.0V
-7.0V
1
0246810
-I
, DRAIN CURRENT (A)
D
-10V
Figure 2. On-Resistance Variation
with Drain Current and Gate V oltage.
0.5
ID=-1.0A
0.4
0.3
, ON-RESISTANCE (OHM)
0.2
DS(ON)
R
0.1
2345678910
-V
, GATE TO SOURCE VOLTAGE (V)
GS
TJ=125oC
25oC
Figure 3. On-Resistance Variation
with Temperature.
4
VDS=-5V
3
2
, DRAIN CURRENT (A)
1
D
-I
0
12345
-V
, GATE TO SOURCE VOLTAGE (V)
GS
T
=-55oC
125
25oC
o
Figure 5. Transfer Characteristics.
Figure 4. On-Resistance Variation
with Gate-to-Source Voltage.
10
VGS=0
1
TJ=125oC
0.1
0.01
, REVERSE DRAIN CURRENT (A)
S
-I
0.001
0 0.3 0.6 0.9 1.2 1.5
25oC
-55oC
-V
, BODY DIODE VOLTAGE (V)
SD
Figure 6. Body Diode Forward V oltage
Variation with Source Current
and Temperature.
FDC6506P Rev. C
Typical Characteristics (continued)
FDC6506P
10
ID= -1.8A
8
6
4
2
, GATE-SOURCE VOLTAGE (V)
GS
-V
0
01234
, GATE CHARGE (nC)
Q
g
VDS=-5.0V
-
-15V
300
240
C
180
120
CAPACITANCE (pF)
60
0
0 6 12 18 24 30
, DRAIN TO SOURCE VOLTAGE (V)
-V
DS
iss
C
oss
C
rss
Figure 7. Gate-Charge Characteristics. Figure 8. Capacitance Characteristics.
30
10
3
RDS(ON) LIMIT
1
0.3
V = -10V
GS
0.1
SINGLE PULSE
D
-I , DRAIN CURRENT (A)
R = 180°C/W
JA
θ
0.03
0.01
T = 25°C
A
0.1 0.2 0.5 1 2 5 10 20 50
-V , DRAIN-SOURCE VOLTAGE (V)
DS
1ms
10ms
100ms
1s
DC
100us
5
4
SINGLE PULSE
R =180°C/W
JA
θ
T = 25°C
A
3
2
POWER (W)
1
0
0.01 0.1 1 10 100 300
SINGLE PULSE TIME (SEC)
f=1MHz
=0V
V
GS
Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
0.5
0.2
0.2
0.1
0.1
0.05
0.05
0.02
r(t), NORMALIZED EFFECTIVE
0.02
TRANSIENT THERMAL RESISTANCE
0.01
0.01
Single Pulse
0.0001 0.001 0.01 0.1 1 10 100 300
t , TIME (sec)
1
R (t) = r(t) * R
JA
θ
R =
180
JA
θ
P(pk)
t
1
t
2
T - T = P * R (t)
J
A
Duty Cycle, D = t / t
°C/W
JA
θ
JA
θ
2
1
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1c.
Transient themal response will change depending on the circuit board design.
FDC6506P Rev. C
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
CoolFET™
CROSSVOLT™
E2CMOS
TM
FACT™
FACT Quiet Series™
®
FAST
FASTr™
GTO™
HiSeC™
ISOPLANAR™
MICROWIRE™
POP™
PowerTrench™
QS™
Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
TinyLogic™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
Formative or
In Design
First Production
Full Production
Not In Production
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
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