Fairchild FDC6506P service manual
FDC6506P
Dual P-Channel Logic Level PowerT rench MOSFET
General Description
These P-Channel logic level MOSFET s are produced using
Fairchild Semiconductor's advanced PowerTrench
process that has been especially tailored to minimize
on-state resistance and yet maintain low gate charge for
superior switching performance.
These devices have been designed to offer exceptional
power dissipation in a very small footprint for applications
where the bigger more expensive SO-8 and TSSOP-8
packages are impractical.
Applications
• Load switch
• Battery protection
• Power management
Features
• -1.8 A, -30 V. R
R
DS(on)
DS(on)
• Low gate charge (2.3nC typical).
• Fast switching speed.
• High performance trench technology for extremely
low R
• SuperSOT
than standard SO-8); low profile (1mm thick).
.
DS(ON)
TM
-6 package: small footprint (72% smaller
= 0.170 Ω @ V
= 0.280 Ω @ V
February 1999
= -10 V
GS
= -4.5 V
GS
FDC6506P
D2
S1
4
3
D1
5
2
G2
SuperSOT -6
TM
S2
G1
Absolute Maximum Ratings
6
TA = 25°C unless otherwise noted
1
Symbol Parameter Ratings Units
V
DSS
V
GSS
I
D
P
D
TJ, T
stg
Drain-Source Voltage -30 V
Gate-Source Voltage
Drain Current - Continuous
- Pulsed -10
Power Dissipation for Si ngl e Operati on
Operating and Storage Junction Temperature Range -55 to +150
(Note 1a)
(Note 1a)
(Note 1b)
(Note 1c)
20 V
±
-1.8 A
0.96 W
0.9
0.7
C
°
Thermal Characteristics
R
JA
θ
R
JC
θ
Thermal Resistance, Junct i on-to-A m bi ent
Thermal Resistance, Junct i on-to-Cas e
(Note 1a)
(Note 1)
130
60
C/W
°
C/W
°
Package Outlines and Ordering Information
Device Marking Device Reel Size Tape Width Quantity
506
.
1999 Fairchild Semiconductor Corporation
FDC6506P 7’’ 8mm 3000 units
FDC6506P Rev. C
FDC6506P
yp
Electrical Characteristics
TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min T
Off Characteristics
BV
DSS
BV
∆
T
∆
I
DSS
I
GSSF
I
GSSR
On Characteristics
V
GS(th)
GS(th)
V
∆
T
∆
R
DS(on)
I
D(on)
g
FS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA-30 V
Breakdown Voltage Temperature
DSS
Coefficient
J
ID = -250 µA, Referenced to 25°C-20 mV/
Zero Gate Voltage Drain Current VDS = -24 V, VGS = 0 V -1
Gate-Body Leakage Current, Forward VGS = 20 V, VDS = 0 V 100 nA
Gate-Body Leakage Current, Reverse VGS = -20 V, VDS = 0 V -100 nA
(Note 2)
Gate Threshold Voltage VDS = VGS, ID = -250 µA-1-1.8-3V
Gate Threshold Voltage
Temperature Coefficient
J
Static Drain-Source
On-Resistance
ID = -250 µA, Referenced to 25°C4 mV/
VGS = -10 V, ID = -1.8 A
V
= -10 V, ID = -1.8 A @125°C
GS
V
= -4.5 V, ID = -1.4 A
GS
On-State Drain Current VGS = -10 V, VDS = - 5 V -10 A
Forward Transconductance VDS = -5 V, ID = -1.8 A 3 S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance 190 pF
Output Capacitance 70 pF
Reverse Transfer Capacitance
V
= -15 V, VGS = 0 V,
DS
f = 1.0 MHz
Max Units
0.17
0.14
0.27
0.20
0.28
0.22
30 pF
C
°
A
µ
C
°
Ω
(Note 2)
Switching Characteristics
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
g
gs
gd
Turn-On Delay Time 7 14 ns
Turn-On Rise Time 8 16 ns
Turn-Off Delay Time 14 25 ns
Turn-Off Fall Time
Total Gate Charge 2.3 3.5 nC
Gate-Source Charge 1 nC
Gate-Drain Charge
V
= -15 V, ID = -1 A,
DD
V
= -4.5 V, R
GS
V
= -5 V, ID = -1.8 A,
DS
V
= -10 V
GS
GEN
= 6
Ω
26ns
0.8 nC
Drain-Source Diode Characteristics and Maximum Ratings
I
S
V
SD
Notes:
1. R
θJA
of the drain pins. R
sharing the dissipated heat energy equally.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%
Maximum Continuous Drain-Source Di ode Forward Current -0.8 A
Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.8 A
is the sum of the junction-to-case and case-to-ambient resistance where the case thermal reference is defined as the solder mounting surface
is guaranteed by design while R
θJC
a) 130 °C/W when
mounted on a 0.125 in
pad of 2 oz. copper.
is determined by the user's board design.Both devices are assumed to be operating and
θJA
2
b) 140 °C/W when
mounted on a 0.005 in
pad of 2 oz. copper.
(Note 2)
2
-0.8 -1.2 V
c) 180 °C/W when
mounted on a 0.0015 in
pad of 2 oz. copper.
2
FDC6506P Rev. C
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