Fairchild FDC6333C service manual
FDC6333C
G2
FDC6333C
30V N & P-Channel PowerTrench MOSFETs
October 2001
General Description
These N & P-Channel MOSFETs are produced using
Fairchild Semiconductor’s advanced PowerTrench
process that has been especially tailored to minimize
on-state resistance and yet maintain superior
switching performance.
These devices have been designed to offer
exceptional power dissipation in a very small footprint
for applications where the bigger more expensive
SO-8 and TSSOP-8 packages are impractical.
Applications
• DC/DC converter
• Load switch
Features
• Q1 2.5 A, 30V. R
• Q2 –2.0 A, 30V. R
• Low gate charge
• High performance trench technology for extremely
low R
DS(ON)
.
• SuperSOT –6 package: small footprint (72% smaller than
SO-8); low profile (1mm thick).
= 95 mΩ @ VGS = 10 V
DS(ON)
R
= 150 mΩ @ VGS = 4.5 V
DS(ON)
= 150 mΩ @ VGS = –10 V
DS(ON)
R
= 220 mΩ @ VGS = –4.5 V
DS(ON)
• LCD display inverter
D2
S1
D1
G1
S2
SuperSOT -6
TM
Pin 1
SuperSOT™-6
Absolute Maximum Ratings T
=25oC unless otherwise noted
A
4
5
6
Q2(P)
3
2
1
Q1(N)
Symbol Parameter Q1 Q2 Units
V
DSS
V
GSS
I
D
P
D
TJ, T
STG
Drain-Source Voltage 30 –30 V
Gate-Source Voltage ±16 ±25 V
Drain Current – Continuous (Note 1a) 2.5 –2.0 A
– Pulsed 8 –8
Power Dissipation for Single Operation (Note 1a) 0.96
(Note 1b)
(Note 1c)
0.9
0.7
Operating and Storage Junction Temperature Range –55 to +150
W
°C
Thermal Characteristics
R
θJA
R
θJC
Thermal Resistance, Junction-to-Ambient (Note 1a) 130
Thermal Resistance, Junction-to-Case (Note 1) 60
Package Marking and Ordering Information
Device Marking Device Reel Size Tape width Quantity
.333 FDC6333C 7’’ 8mm 3000 units
2001 Fairchild Semiconductor Corporation
°C/W
°C/W
FDC6333C Rev C (W)
FDC6333C
Electrical Characteristics T
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Off Characteristics
BV
DSS
∆BVDSS
∆T
J
I
DSS
I
GSSF
I
GSSR
Drain–Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage, Forward
Gate–Body Leakage, Reverse
VGS = 0 V, ID = 250 µA
VGS = 0 V, ID = –250 µA
ID = 250 µA,Ref. to 25°C
ID = –250 µA,Ref. to 25°C
VDS = 24 V, VGS = 0 V
VDS = –24 V, VGS = 0 V Q1Q2
VGS = 16 V, VDS = 0 V
VGS = 25 V, VDS = 0 V Q1Q2
VGS = –16 V, VDS = 0 V
VGS = –25 V, VDS = 0 V Q1Q2
Q1Q230
–30
Q1
Q2
27
–22
1
–1
100
100
–100
–100
V
mV/°C
µA
nA
nA
On Characteristics (Note 2)
V
GS(th)
∆VGS(th)
∆T
J
R
DS(on)
I
D(on)
g
FS
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
Forward Transconductance
VDS = VGS, ID = 250 µA
Q1
VDS = VGS, ID = –250 µA
Q2
ID = 250 µA,Ref. To 25°C
Q1
ID = –250 µA,Ref. to 25°C
Q2
VGS = 10 V, ID = 2.5 A
Q1
VGS = 4.5 V, ID = 2.0 A
VGS = 10 V, ID = 2.5 A,TJ=125°C
VGS = –10 V, ID = –2.0 A
Q2
VGS =– 4.5 V, ID = –1.7 A
VGS = 10 V, ID= –2.0 A,TJ=125°C
VGS = 10 V, VDS = 5 V
Q1
VGS = –10 V, VDS = –5 V
Q2
VDS = 5 V ID = 2.5 A
Q1
VDS = –5 V ID = –2.0A
Q2
1 1.8 3Gate Threshold Voltage
–1 –1.8 –3
4
–4
73
90
106
95
142
149
95
150
148
130
220
216
8On–State Drain Current
–8
7
3
V
mV/°C
mΩ
A
S
Dynamic Characteristics
C
iss
C
oss
C
rss
Input Capacitance
Q1
Q2
Q1
Q2
Q1
Q2
VDS=15 V, V
VDS=–15 V, V
VDS=15 V, V
VDS=–15 V, V
VDS=15 V, V
VDS=–15 V, V
= 0 V, f=1.0MHz
GS
= 0 V, f=1.0MHz
GS
= 0 V, f=1.0MHz
GS
= 0 V, f=1.0MHz
GS
= 0 V, f=1.0MHz
GS
= 0 V, f=1.0MHz
GS
282
185
49Output Capacitance
56
20Reverse Transfer Capacitance
26
pF
pF
pF
Switching Characteristics (Note 2)
t
t
t
t
Q
Q
Q
d(on)
r
d(off)
f
Turn–On Delay Time
Turn–On Rise Time
Turn–Off Delay Time
Turn–Off Fall Time
Q1
For Q1:
V
Q2
VGS= 10 V, R
Q1
Q2
For Q2:
V
Q1
VGS= –10 V, R
Q2
Q1
=15 V, I
DS
=–15 V, I
DS
DS
GEN
DS
GEN
= 1 A
= 6 Ω
= –1 A
= 6 Ω
Q2
g
gs
gd
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
Q1
For Q1:
V
Q2
VGS= 10 V, R
Q1
For Q2:
Q2
V
Q1
VGS= –10 V,
=15 V, I
DS
=–15 V, I
DS
= 2.5 A
DS
GEN
= –2.0 A
DS
= 6 Ω
Q2
4.5 9
4.5 9
6 12
13 23
19 34
11 20
1.5 3
2 4
4.7 6.6
4.1 5.7
0.9
0.8
0.6
0.4
ns
ns
ns
ns
nC
nC
nC
FDC6333C Rev C (W)
Electrical Characteristics T
FDC6333C
= 25°C unless otherwise noted
A
Symbol Parameter Test Conditions Min Typ Max Units
Drain–Source Diode Characteristics and Maximum Ratings
I
S
Maximum Continuous Drain–Source Diode Forward Current Q1
Q2
V
SD
Drain–Source Diode Forward
Voltage
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
the drain pins. R
is guaranteed by design while R
θJC
is determined by the user's board design.
θCA
VGS = 0 V, IS = 0.8 A (Note 2)
Q1
VGS = 0 V, IS = 0.8 A (Note 2)
Q2
0.8 1.2
0.8 –1.2
0.8
–0.8
A
V
a) 130 °C/W when
mounted on a 0.125
in2 pad of 2 oz.
copper.
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
b) 140°/W when mounted
on a .004 in2 pad of 2 oz
copper
c) 180°/W when mounted on a
minimum pad.
FDC6333C Rev C (W)
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