Fairchild FDC6321C service manual

April 1999

FDC6321C
Dual N & P Channel , Digital FET

General Description Features

These dual N & P Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This very
high density process is especially tailored to minimize
on-state resistance. This device has been designed
especially for low voltage applications as a replacement for
digital transistors in load switching applications. Since bias
resistors are not required this dual digital FET can replace
several digital transistors with different bias resistors.

N-Ch 25 V, 0.68 A, R
P-Ch -25 V, -0.46 A, R

= 0.45 Ω @ VGS= 4.5 V

DS(ON)

= 1.1 Ω @ VGS= -4.5 V.

DS(ON)

Very low level gate drive requirements allowing direct
operation in 3 V circuits. V

GS(th)

< 1.0V.

Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model

Replace multiple dual NPN & PNP digital transistors.

SOT-23

SuperSOTTM-6

Mark:.321

SuperSOTTM-8

SO-8

SOT-223

SOIC-16

D2

S1

4

3

D1

5

2

G2

SuperSOT -6

TM

Absolute Maximum Ratings T

Symbol Parameter N-Channel P-Channel Units

V

, VCCDrain-Source Voltage, Power Supply Voltage 25 -25 V

DSS

V

, VINGate-Source Voltage, 8 -8 V

GSS

ID, I

P

D

TJ,T
ESD Electrostatic Discharge Rating MIL-STD-883D

THERMAL CHARACTERISTICS

R

JA

θ

R

JC

θ

Drain/Output Current - Continuous 0.68 -0.46 A

O

- Pulsed 2 -1.5

Maximum Power Dissipation (Note 1a)
(Note 1b)

Operating and Storage Tempature Ranger -55 to 150 °C

STG

Human Body Model (100pf / 1500 Ohm)

Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W

S2

G1

= 25oC unless other wise noted

A

6

1

0.9 W

0.7

6 kV

© 1999 Fairchild Semiconductor Corporation

FDC6321C.RevB

Electrical Characteristics (T

= 25 OC unless otherwise noted )

A

Symbol Parameter Conditions
OFF CHARACTERISTICS

BV

DSS

Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA N-Ch 25 V

VGS = 0 V, ID = -250 µA P-Ch -25

∆BV

DSS

Breakdown Voltage Temp. Coefficient ID= 250 µA, Referenced to 25 oC N-Ch 26 mV /oC

/∆T

J

ID = -250 µA, Referenced to 25 oC P-Ch -22

I

DSS

I

DSS

I

GSS

Zero Gate Voltage Drain Current VDS= 20 V, VGS= 0 V, N-Ch 1 µA

Zero Gate Voltage Drain Current VDS =-20 V, V

Gate - Body Leakage Current VGS = 8 V, VDS= 0 V N-Ch 100 nA

VGS = -8 V, VDS= 0 V P-Ch -100 nA

ON CHARACTERISTICS (Note 2)

∆V

GS(th)

Gate Threshold Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 o C N-Ch -2.6 mV / oC

/∆T

J

ID= -250 µA, Referenced to 25 o C P-Ch 2.1

V

GS(th)

Gate Threshold Voltage VDS = VGS, ID = 250 µA N-Ch 0.65 0.8 1.5 V

VDS = VGS, ID= -250 µA P-Ch -0.65 -0.86 -1.5

R

DS(ON)

Static Drain-Source On-Resistance VGS = 4.5 V, ID = 0.5 A N-Ch 0.33 0.45

VGS = 2.7 V, ID = 0.25A 0.44 0.6
VGS = -4.5 V, ID = -0.5 A P-Ch 0.87 1.1

VGS = -2.7 V, ID = -0.25 A 1.22 1.5

I

D(ON)

On-State Drain Current VGS = 4.5 V, VDS = 5 V N-Ch 1 A

VGS = -4.5 V, VDS = -5 V P-Ch -1

g

FS

Forward Transconductance VDS = 5 V, ID= 0.5 A N-Ch 1.45 S

VDS = -5 V, ID= -0.5 A P-Ch 0.8

DYNAMIC CHARACTERISTICS

C

iss

Input Capacitance N-Channel N-Ch 50 pF

VDS= 10 V, VGS= 0 V, P-Ch 63

C

oss

Output Capacitance f = 1.0 MHz N-Ch 28 pF

P-Channel P-Ch 34

C

rss

Reverse Transfer Capacitance VDS= -10 V, VGS = 0V, N-Ch 9 pF

f = 1.0 MHz P-Ch 10

Min Typ Max Units

Type

TJ = 55°C 10

= 0 V, P-Ch -1 µA

GS

TJ = 55°C -10

TJ =125°C 0.51 0.72

TJ =125°C 1.21 1.8

Ω

FDC6321C.RevB

Electrical Characteristics (T

= 25 OC unless otherwise noted )

A

SWITCHING CHARACTERISTICS (Note 2)
Symbol Parameter Conditions

t

D(on)

Turn - On Delay Time N-Channel N-Ch 3 6 nS

Type

Min Typ Max Units

VDD = 6 V, ID = 0.5 A, P-Ch 7 20

t

r

Turn - On Rise Time

VGs = 4.5 V, R

= 50 Ω

GEN

N-Ch 8 16 nS
P-Ch 9 18

t

D(off)

Turn - Off Delay Time P-Channel N-Ch 17 30 nS

VDD = -6 V, ID = -0.5 A, P-Ch 55 110

t

f

Turn - Off Fall Time

V

= -4.5 V, R

Gen

GEN

= 50 Ω

N-Ch 13 25 nS
P-Ch 35 70

Q

g

Total Gate Charge N-Channel N-Ch 1.64 2.3 nC

VDS= 5 V, ID = 0.5 A, P-Ch 1.1 1.5

Q

gs

Gate-Source Charge VGS = 4.5 V N-Ch 0.38 nC

P- Channel P-Ch 0.32

Q

gd

Gate-Drain Charge VDS = -5 V, N-Ch 0.45 nC

ID = -0.25 A, VGS = -4.5 V P-Ch 0.25

DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS

I

S

Maximum Continuous Drain-Source Diode Forward Current N-Ch 0.3 A

P-Ch -0.5

V

SD

Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.5 A

(Note) N-Ch 0.83 1.2 V

TJ =125°C 0.69 0.85

VGS = 0 V, IS = -0.5 A

(Note) P-Ch -0.89 -1.2

TJ =125°C -0.75 -0.85

Notes:

1. R

is the sum of the junction-to-case and case-to-ambient thermal resistance where thecase thermal reference is defined as the solder mounting surface of the drain pins. R

JA

θ

by design while R

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.

is determined by the user's board design.

CA

θ

is guaranteed

JC

θ

a. 140OC/W on a 0.125 in2 pad of

2oz copper.

b. 180OC/W on a 0.005 in2 of pad

of 2oz copper.

FDC6321C.RevB