Fairchild FDC6304P service manual
July 1997
FDC6304P
Digital FET, Dual P-Channel
General Description Features
These P-Channel enhancement mode field effect transistor are
produced using Fairchild's proprietary, high cell density, DMOS
technology. This very high density process is tailored to minimize
on-state resistance at low gate drive conditions. This device is
designed especially for application in battery power applications
such as notebook computers and cellular phones. This device
has excellent on-state resistance even at gate drive voltages as
low as 2.5 volts.
SOT-23
SuperSOTTM-6
Mark: .304
SuperSOTTM-8
-25 V, -0.46 A continuous, -1.0 A Peak.
R
= 1.5 Ω @ VGS= -2.7 V
R
DS(ON)
= 1.1 Ω @ V
DS(ON)
= -4.5 V.
GS
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model.
SO-8
SOT-223
4
5
6
SOIC-16
3
2
1
Absolute Maximum Ratings T
= 25oC unless other wise noted
A
Symbol Parameter FDC6304P Units
V
DSS
V
GSS
I
D
Drain-Source Voltage -25 V
Gate-Source Voltage -8 V
Drain Current - Continuous -0.46 A
- Pulsed -1
P
D
Maximum Power Dissipation (Note 1a) 0.9 W
(Note 1b) 0.7
TJ,T
ESD Electrostatic Discharge Rating MIL-STD-883D
Operating and Storage Temperature Range -55 to 150 °C
STG
6.0 kV
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
FDC6304P Rev.D
Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
I
GSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA -25 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
ID = -250 µA, Referenced to 25 o C
VDS = -20 V, V
GS
= 0 V
-22
-1 µA
TJ = 55°C
Gate - Body Leakage Current VGS = -8 V, VDS= 0 V -100 nA
mV /o C
-10 µA
ON CHARACTERISTICS (Note 2)
∆V
V
R
GS(th)
DS(ON)
GS(th)
Gate Threshold Voltage Temp. Coefficient
/∆T
J
Gate Threshold Voltage
ID = -250 µA, Referenced to 25 o C
VDS = VGS, ID = -250 µA
-0.65 -0.86 -1.5 V
Static Drain-Source On-Resistance VGS = -2.7 V, ID = -0.25 A 1.22 1.5
VGS = -4.5 V, ID = -0.5 A
2.1
0.87 1.1
mV /o C
TJ =125°C 1.21 2
I
D(ON)
On-State Drain Current
VGS = -2.7 V, VDS = -5 V
-0.5 A
VGS = -4.5 V, VDS = -5 V -1
g
FS
Forward Transconductance
VDS = -5 V, ID= -0.5 A
0.8 S
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance VDS = -10 V, VGS = 0 V,
Output Capacitance 35 pF
f = 1.0 MHz
62 pF
Reverse Transfer Capacitance 9.5 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 8 20 ns
VDD = -6 V, ID = -0.5 A,
VGS = -4.5 V, R
GEN
= 50 Ω
Turn - Off Delay Time 55 110 ns
Turn - Off Fall Time 35 70 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 0.32 nC
Gate-Drain Charge 0.28 nC
VDS = -5 V, ID = - 0.25 A,
VGS = -4.5 V
7 20 ns
1.1 1.5 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
JA
θ
design while R
Maximum Continuous Drain-Source Diode Forward Current -0.5 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design.
CA
θ
VGS = 0 V, IS = -0.5 A
(Note 2)
-0.88 -1.2 V
is guaranteed by
JC
θ
Ω
a. 140OC/W on a 0.125 in2 pad of
2oz copper.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
b. 180OC/W on a 0.005 in2 of pad
of 2oz copper.
FDC6304P Rev.D
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