Fairchild FDC6303N service manual
FDC6303N
Digital FET, Dual N-Channel
General Description Features
August 1997
These dual N-Channel logic level enhancement mode field
effect transistors are produced using Fairchild's proprietary,
high cell density, DMOS technology. This very high density
process is especially tailored to minimize on-state
resistance. This device has been designed especially for
low voltage applications as a replacement for digital
transistors in load switching applications. Since bias
resistors are not required this one N-Channel FET can
replace several digital transistors with different bias
resistors like the IMHxA series.
SOT-23
SuperSOTTM-6
Mark: .303
SuperSOTTM-8
25 V, 0.68 A continuous, 2 A Peak.
R
= 0.6 Ω @ V
DS(ON)
R
= 0.45 Ω @ VGS= 4.5 V.
DS(ON)
= 2.7 V
GS
Very low level gate drive requirements allowing direct
operation in 3V circuits. V
GS(th)
< 1.5 V.
Gate-Source Zener for ESD ruggedness.
>6kV Human Body Model
Replace multiple NPN digital transistors (IMHxA series)
with one DMOS FET.
SO-8
SOT-223
4
5
6
SOIC-16
3
2
1
Absolute Maximum Ratings T
= 25°C unless otherwise noted
A
Symbol Parameter FDC6303N Units
V
DSS
V
GSS
I
D
Drain-Source Voltage 25 V
Gate-Source Voltage 8 V
Drain Current - Continuous 0.68 A
- Pulsed 2
P
D
Maximum Power Dissipation (Note 1a) 0.9 W
(Note 1b) 0.7
TJ,T
ESD Electrostatic Discharge Rating MIL-STD-883D
Operating and Storage Temperature Range -55 to 150 °C
STG
6.0 kV
Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS
R
JA
θ
R
JC
θ
© 1997 Fairchild Semiconductor Corporation
Thermal Resistance, Junction-to-Ambient (Note 1a) 140 °C/W
Thermal Resistance, Junction-to-Case (Note 1) 60 °C/W
FDC6303N Rev.C
DMOS Electrical Characteristics (T
= 25 OC unless otherwise noted )
A
Symbol Parameter Conditions Min Typ Max Units
OFF CHARACTERISTICS
BV
∆BV
I
DSS
DSS
DSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA 25 V
Breakdown Voltage Temp. Coefficient
/∆T
J
Zero Gate Voltage Drain Current
ID = 250 µA, Referenced to 25 o C
VDS = 20 V, V
GS
= 0 V
26
1 µA
mV /o C
TJ = 55°C 10 µA
I
GSS
Gate - Body Leakage Current
VGS = 8 V, VDS= 0 V
100 nA
ON CHARACTERISTICS (Note 2)
∆V
V
R
GS(th)
GS(th)
DS(ON)
Gate Threshold Voltage Temp.Coefficient
/∆T
J
ID = 250 µA, Referenced to 25 o C
Gate Threshold Voltage VDS = VGS, ID = 250 µA 0.65 0.8 1.5 V
Static Drain-Source On-Resistance
VGS = 4.5 V, ID = 0.5 A
TJ =125°C
-2.6
0.33 0.45
0.52 0.8
mV /o C
Ω
VGS = 2.7 V, ID = 0.2 A 0.44 0.6
I
g
D(ON)
FS
On-State Drain Current
VGS = 2.7 V, VDS = 5 V
Forward Transconductance VDS = 5 V, ID= 0.5 A 1.45 S
0.5 A
DYNAMIC CHARACTERISTICS
C
iss
C
oss
C
rss
Input Capacitance
Output Capacitance 28 pF
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
Reverse Transfer Capacitance 9 pF
50 pF
SWITCHING CHARACTERISTICS (Note 2)
t
t
t
t
Q
Q
Q
D(on)
r
D(off)
f
Turn - On Delay Time
Turn - On Rise Time 8.5 18 ns
VDD = 6 V, ID = 0.5 A,
VGS = 4.5 V, R
GEN
= 50 Ω
Turn - Off Delay Time 17 30 ns
Turn - Off Fall Time 13 25 ns
g
gs
gd
Total Gate Charge
Gate-Source Charge 0.38 nC
Gate-Drain Charge 0.45 nC
VDS = 5 V, ID = 0.5 A,
VGS = 4.5 V
3 6 ns
1.64 2.3 nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
V
SD
Notes:
1. R
JA
θ
design while R
Maximum Continuous Source Current 0.3 A
Drain-Source Diode Forward Voltage
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R
is determined by the user's board design. R
CA
θ
shown below for single device operation on FR-4 in still air.
JA
θ
VGS = 0 V, IS = 0.5 A (Note 2)
0.83 1.2 V
is guaranteed by
JC
θ
a. 140OC/W on a 0.125 in2 pad of
2oz copper.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
b. 180OC/W on a 0.005 in2 of pad
of 2oz copper.
FDC6303N Rev.C
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