Fairchild FAN3223, FAN3224, FAN3225 service manual

FAN3223 / FAN3224 / FAN3225 Dual 4A High-Speed, Low-Side Gate Drivers

Features

 Industry-Standard Pinouts  4.5 to 18V Operating Range  5A Peak Sink/Source at V  4.3A Sink / 2.8A Source at V

DD

= 12V

= 6V

OUT

 Choice of TTL or CMOS Input Thresholds  Three Versions of Dual Independent Drivers:

- Dual Inverting + Enable (FAN3223)

- Dual Non-Inverting + Enable (FAN3224)

- Dual-Inputs (FAN3225)

 Internal Resistors Turn Driver Off If No Inputs  MillerDrive™ Technology  12ns / 9ns Typical Rise/Fall Times with 2.2nF Load  Typical Propagation Delay Under 20ns Matched

within 1ns to the Other Channel

 Double Current Capability by Paralleling Channels  8-Lead 3x3mm MLP or 8-Lead SOIC Package  Rated from –40°C to +125°C Ambient

Applications

Switch-Mode Power Supplies

  High-Efficiency MOSFET Switching  Synchronous Rectifier Circuits  DC-to-DC Converters  Motor Control

Description

The FAN3223-25 family of dual 4A gate drivers is designed to drive N-channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals. The driver is available with either TTL or CMOS input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output LOW until the supply voltage is within the operating range. In addition, the drivers feature matched internal propagation delays between A and B channels for applications requiring dual gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two drivers in parallel to effectively double the current capability driving a single MOSFET.

The FAN322X drivers incorporate MillerDrive™ architecture for the final output stage. This bipolarMOSFET combination provides high current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability.

The FAN3223 offers two inverting drivers and the FAN3224 offers two non-inverting drivers. Each device has dual independent enable pins that default to ON if not connected. In the FAN3225, each channel has dual inputs of opposite polarity, which allows configuration as non-inverting or inverting with an optional enable function using the second input. If one or both inputs are left unconnected, internal resistors bias the inputs such that the output is pulled LOW to hold the power MOSFET OFF.

Related Resources

AN-6069 — Application Review and Comparative Evaluation of Low-Side Gate Drivers

FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers

July 2012

FAN3223 FAN3224 FAN3225

Figure 1. Pin Configurations

Ordering Information

FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers

Part Number Logic

FAN3223CMPX

FAN3223CMX SOIC-8 Tape & Reel 2,500

FAN3223TMPX

FAN3223TMX SOIC-8 Tape & Reel 2,500

FAN3224CMPX

FAN3224CMX SOIC-8 Tape & Reel 2,500

FAN3224TMPX

FAN3224TMX SOIC-8 Tape & Reel 2,500

FAN3225CMPX

FAN3225CMX SOIC-8 Tape & Reel 2,500

FAN3225TMPX

FAN3225TMX SOIC-8 Tape & Reel 2,500

Dual Inverting Channels + Dual Enable

Dual Non-Inverting Channels + Dual Enable

Dual Channels of Two-Input / OneOutput Drivers

Input

Threshold

CMOS

TTL

CMOS

TTL

CMOS

TTL

Package

3x3mm MLP-8 Tape & Reel 3,000

Packing

Method

Quantity per Reel

Package Outlines

Figure 2. 3x3mm MLP-8 (Top View) Figure 3. SOIC-8 (Top View)

Thermal Characteristics

Package

8-Lead 3x3mm Molded Leadless Package (MLP)

8-Pin Small Outline Integrated Circuit (SOIC)

(1)

(2)



JL

1.2 64 42 2.8 0.7 °C/W

38 29 87 41 2.3 °C/W

(3)



JT

JA

(4)



JB

(5)



JT

Notes:

1. Estimates derived from thermal simulation; actual values depend on the application.



2. Theta_JL ( thermal pad) that are typically soldered to a PCB.

3. Theta_JT ( held at a uniform temperature by a top-side heatsink.

4. Theta_JA (Θ The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.

5. Psi_JB ( application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.

6. Psi_JT ( the center of the top of the package for the thermal environment defined in Note 4.

): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any

JL



): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is

JT

): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.

JA



): Thermal characterization parameter providing correlation between semiconductor junction temperature and an

JB



): Thermal characterization parameter providing correlation between the semiconductor junction temperature and

JT

(6)

Units

FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers

FAN3223 FAN3224 FAN3225

Figure 4. PinAssignments (Repeated)

Pin Definitions

Name Pin Description

ENA

ENB

GND

INA

INA+

INA-

INB

INB+

INB-

OUTA

OUTB

OUTA

OUTB

VDD

Enable Input for Channel A. Pull pin LOW to inhibit driver A. ENA has TTL thresholds for both TTL and CMOS INx threshold.

Enable Input for Channel B. Pull pin LOW to inhibit driver B. ENB has TTL thresholds for both TTL and CMOS INx threshold.

Ground. Common ground reference for input and output circuits.

Input to Channel A.

Non-Inverting Input to Channel A. Connect to VDD to enable output.

Inverting Input to Channel A. Connect to GND to enable output.

Input to Channel B.

Non-Inverting Input to Channel B. Connect to VDD to enable output.

Inverting Input to Channel B. Connect to GND to enable output.

Gate Drive Output A: Held LOW unless required input(s) are present and V

Gate Drive Output B: Held LOW unless required input(s) are present and V

is above UVLO threshold.

DD

is above UVLO threshold.

DD

Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is above UVLO threshold.

Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is above UVLO threshold.

Thermal Pad (MLP only). Exposed metal on the bottom of the package; may be left floating or connected

P1

to GND; NOT suitable for carrying current.

Supply Voltage. Provides power to the IC.

Output Logic

FAN3223 (x=A or B) FAN3224 (x=A or B) FAN3225 (x=A or B)

ENx INx

OUTx

0 0 0 0 0

0 1

(7)

1

0 1 1

(7)

1

(7)

0 0 1 0 0

(7)

0 1

Note:

7. Default input signal if no external connection is made.

ENx INx OUTx INx+ INx− OUTx

(7)

0 0

(7)

0

(7)

1 1 1 1

(7)

0 1 0 1

(7)

0 0

(7)

1

(7)

0

(7)

0

Block Diagrams

FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers

Figure 5. FAN3223 Block Diagram

Figure 6. FAN3224 Block Diagram

Block Diagrams

FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers

Figure 7. FAN3225 Block Diagram

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDD VDD to PGND -0.3 20.0 V

VEN ENA and ENB to GND GND - 0.3 VDD + 0.3 V

VIN INA, INA+, INA–, INB, INB+ and INB– to GND GND - 0.3 VDD + 0.3 V

V

OUTA and OUTB to GND GND - 0.3 VDD + 0.3 V

OUT

TL Lead Soldering Temperature (10 Seconds) +260 ºC

TJ Junction Temperature -55 +150 ºC

T

Storage Temperature -65 +150 ºC

STG

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers

Symbol Parameter Min. Max. Unit

VDD Supply Voltage Range 4.5 18.0 V

VEN Enable Voltage ENA and ENB 0 VDD V

VIN Input Voltage INA, INA+, INA–, INB, INB+ and INB– 0 VDD V

TA Operating Ambient Temperature -40 +125 ºC

FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers

Electrical Characteristics

Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device.

Symbol Parameter Conditions Min. Typ. Max. Unit

Supply

VDD Operating Range 4.5 18.0 V

IDD

Supply Current, Inputs / EN Not Connected

VON Turn-On Voltage INA=ENA=VDD, INB=ENB=0V 3.5 3.9 4.3 V

V

Turn-Off Voltage INA=ENA=VDD, INB=ENB=0V 3.3 3.7 4.1 V

OFF

Inputs (FAN322xT)

V

INx Logic Low Threshold 0.8 1.2 V

INL_T

V

INx Logic High Threshold 1.6 2.0 V

INH_T

I

Non-inverting Input IN from 0 to VDD -1.5 175.0 µA

IN+

I

Inverting Input IN from 0 to VDD -175.0 1.5 µA

IN-

V

TTL Logic Hysteresis Voltage 0.2 0.4 0.8 V

HYS_T

Inputs (FAN322xC)

V

INx Logic Low Threshold 30 38 %V

INL_C

V

INx Logic High Threshold 55 70 %V

INH_C

I

IN Current, Low IN from 0 to VDD -1 175 µA

INL

I

IN Current, High IN from 0 to VDD -175 1 µA

INH

V

CMOS Logic Hysteresis Voltage 17 %V

HYS_C

(9)

ENABLE (FAN3223C, FAN3223T, FAN3224C, FAN3224T)

V

Enable Logic Low Threshold EN from 5V to 0V 0.8 1.2 V

ENL

V

Enable Logic High Threshold EN from 0V to 5V 1.6 2.0 V

ENH

V

TTL Logic Hysteresis Voltage

HYS_T

RPU Enable Pull-up Resistance

tD3 EN to Output Propagation Delay

tD4 EN to Output Propagation Delay

(10)

0.4 V

(10)

100 kΩ

(11)

All except FAN3225C 0.70 0.95 mA

FAN3225C

(8)

0.21 0.35 mA

0V to 5V EN, 1V/ns Slew Rate 9 17 26 ns

5V to 0V EN, 1V/ns Slew Rate 11 18 28 ns

Continued on the following page…

DD

FAN3223 / FAN3224 / FAN3225 — Dual 4A High-Speed, Low-Side Gate Drivers

Electrical Characteristics (Continued)

Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device.

Symbol Parameter Conditions Min. Typ. Max. Unit

Output

I

OUT Current, Mid-Voltage, Sinking

SINK

I

OUT Current, Mid-Voltage, Sourcing

SOURCE

I

OUT Current, Peak, Sinking

PK_SINK

I

PK_SOURCE

tD1, tD2

OUT Current, Peak, Sourcing

t

Output Rise Time

RISE

t

Output Fall Time

FALL

Output Propagation Delay, CMOS

(12)

Inputs

(11)

C

(10)

C

(10)

C

tD1, tD2 Output Propagation Delay, TTL Inputs

T

DEL.MATCH

Propagation Matching Between Channels

I

Output Reverse Current Withstand

RVS

(10)

Notes:

8. Lower supply current due to inactive TTL circuitry.

9. EN inputs have TTL thresholds; refer to the ENABLE section

10. Not tested in production.

11. See Timing Diagrams of Figure 10 and Figure 11.

12. See Timing Diagrams of Figure 8 and Figure 9.

OUT at VDD/2, C

=0.22µF, f=1kHz

LOAD

OUT at V

(10)

C

LOAD

0 - 12V

(12)

0 - 5VIN, 1V/ns Slew Rate 9 17 29 ns

/2,

DD

=0.22µF, f=1kHz

=0.22µF, f=1kHz 5 A

=0.22µF, f=1kHz -5 A

=2200pF 12 20 ns

=2200pF 9 17 ns

, 1V/ns Slew Rate 10 18 29 ns

IN

INA=INB, OUTA and OUTB at 50% point

4.3 A

-2.8 A

2 4 ns

500 mA