Fairchild FAN3216, FAN3217 service manual

FAN3216 / FAN3217 Dual-2A, High-Speed, Low-Side Gate Drivers
Features
DD
= 12V
= 6V
OUT
TTL Input Thresholds Two Versions of Dual Independent Drivers:
- Dual Inverting (FAN3216)
- Dual Non-Inverting (FAN3217)
Internal Resistors Turn Driver Off If No Inputs MillerDrive™ Technology 12ns / 9ns Typical Rise/Fall Times with 1nF Load Typical Propagation Delay Under 20ns Matched
within 1ns to the Other Channel
Double Current Capability by Paralleling Channels Standard SOIC-8 Package Rated from –40°C to +125°C Ambient
Applications
Switch-Mode Power Supplies High-Efficiency MOSFET Switching Synchronous Rectifier Circuits DC-to-DC Converters Motor Control
Description
The FAN3216 and FAN3217 dual 2A gate drivers are designed to drive N-channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals. They are both available with TTL input thresholds. Internal circuitry provides an under­voltage lockout function by holding the output LOW until the supply voltage is within the operating range. In addition, the drivers feature matched internal propagation delays between A and B channels for applications requiring dual gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two drivers in parallel to effectively double the current capability driving a single MOSFET.
The FAN3216/17 drivers incorporate MillerDrive™ architecture for the final output stage. This bipolar­MOSFET combination provides high current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing rail­to-rail voltage swing and reverse current capability.
The FAN3216 offers two inverting drivers and the FAN3217 offers two non-inverting drivers. Both are offered in a standard 8-pin SOIC package.
FAN3216 FAN3217
Figure 1. Pin Configurations
FAN3216 / FAN3217 — Dual-2A, High-Speed, Low-Side Gate Drivers
July 2012
Ordering Information
Part Number Logic
FAN3216TMX Dual Inverting Channels TTL SOIC-8
FAN3217TMX Dual Non-Inverting Channels TTL SOIC-8
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3216 / FAN3217 • Rev. 1.0.2
Input
Threshold
Package
Packing
Method
Tape & Reel
Tape & Reel
Quantity per Reel
2,500
2,500
Package Outlines
FAN3216 / FAN3217 — Dual-2A, High-Speed, Low-Side Gate Drivers
Figure 2. SOIC-8 (Top View)
Thermal Characteristics
Package
8-Pin Small Outline Integrated Circuit (SOIC)
Notes:
1. Estimates derived from thermal simulation; actual values depend on the application.
2. Theta_JL ( thermal pad) that are typically soldered to a PCB.
3. Theta_JT ( held at a uniform temperature by a top-side heatsink.
4. Theta_JA (Θ The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.
5. Psi_JB ( application circuit board reference point for the thermal environment defined in Note 4. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.
6. Psi_JT ( the center of the top of the package for the thermal environment defined in Note 4.
Θ
): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any
JL
Θ
): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is
JT
): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow.
JA
Ψ
): Thermal characterization parameter providing correlation between semiconductor junction temperature and an
JB
Ψ
): Thermal characterization parameter providing correlation between the semiconductor junction temperature and
JT
(1)
(2)
Θ
JL
40 31 89 43 3.0 °C/W
Θ
(3)
JT
Θ
JA
(4)
Ψ
JB
(5)
Ψ
JT
(6)
Units
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3216 / FAN3217 • Rev. 1.0.2 2
Pin Configurations
(7)
(7)
(7)
(7)
FAN3216 / FAN3217 — Dual-2A, High-Speed, Low-Side Gate Drivers
FAN3216 FAN3217
Figure 3. Pin Configurations (Repeated)
Pin Definitions
Pin Name Pin Description
1
2
3
2
4
7
5
(FAN3216)
5
(FAN3217)
6
7
(FAN3216)
7
(FAN3217)
8
NC
INA
GND
INA
INB
OUTA
OUTB
OUTB
VDD
OUTA
OUTA
NC
No Connect. This pin can be grounded or left floating. Input to Channel A. Ground. Common ground reference for input and output circuits. Input to Channel A. Input to Channel B. Gate Drive Output A: Held LOW unless required input(s) are present and V
UVLO threshold.
Gate Drive Output B (inverted from the input): Held LOW unless required input is
present and V
is above UVLO threshold.
DD
Gate Drive Output B: Held LOW unless required input(s) are present and V
UVLO threshold.
Supply Voltage. Provides power to the IC. Gate Drive Output A (inverted from the input): Held LOW unless required input is
present and V
is above UVLO threshold.
DD
Gate Drive Output A: Held LOW unless required input(s) are present and V
UVLO threshold.
No Connect. This pin can be grounded or left floating.
is above
DD
is above
DD
is above
DD
Output Logic
FAN3216 (x=A or B) FAN3217 (x=A or B)
INx
OUTx
0 0 0
1
0 1 0
0 1 0
1
0 1 1
INx OUTx
0
0
Note:
7. Default input signal if no external connection is made.
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3216 / FAN3217 • Rev. 1.0.2 3
Block Diagrams
FAN3216 / FAN3217 — Dual-2A, High-Speed, Low-Side Gate Drivers
Figure 4. FAN3216 Block Diagram
Figure 5. FAN3217 Block Diagram
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3216 / FAN3217 • Rev. 1.0.2 4
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol Parameter Min. Max. Unit
VDD VDD to PGND -0.3 20.0 V
VIN INA, INA+, INA–, INB, INB+ and INB– to GND GND - 0.3 VDD + 0.3 V
V
OUTA and OUTB to GND GND - 0.3 VDD + 0.3 V
OUT
TL Lead Soldering Temperature (10 Seconds) +260 ºC
TJ Junction Temperature -55 +150 ºC
T
Storage Temperature -65 +150 ºC
STG
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.
FAN3216 / FAN3217 — Dual-2A, High-Speed, Low-Side Gate Drivers
Symbol Parameter Min. Max. Unit
VDD Supply Voltage Range 4.5 18.0 V
VIN Input Voltage INA, INA+, INA–, INB, INB+ and INB– 0 VDD V
TA Operating Ambient Temperature -40 +125 ºC
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3216 / FAN3217 • Rev. 1.0.2 5
FAN3216 / FAN3217 — Dual-2A, High-Speed, Low-Side Gate Drivers
Electrical Characteristics
Unless otherwise noted, VDD=12V, TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device.
Symbol Parameter Conditions Min. Typ. Max. Unit
Supply
VDD Operating Range 4.5 18.0 V
IDD Supply Current, Inputs Not Connected 0.75 1.20 mA
VON Turn-On Voltage INA = VDD, INB = 0V 3.45 3.90 4.35 V
V
Turn-Off Voltage INA = VDD, INB = 0V 3.25 3.70 4.15 V
OFF
Inputs
V
INx Logic Low Threshold 0.8 1.2 V
IL_T
V
INx Logic High Threshold 1.6 2.0 V
IH_T
I
Non-Inverting Input IN from 0 to VDD -1.5 175.0 µA
IN+
I
Inverting Input IN from 0 to VDD -175.0 1.5 µA
IN-
V
TTL Logic Hysteresis Voltage 0.2 0.4 0.8 V
HYS_T
Output
I
OUT Current, Mid-Voltage, Sinking
SINK
I
OUT Current, Mid-Voltage, Sourcing
SOURCE
I
OUT Current, Peak, Sinking
PK_SINK
I
PK_SOURCE
OUT Current, Peak, Sourcing
t
Output Rise Time
RISE
t
Output Fall Time
FALL
(9)
(9)
C
C
(8)
(8)
(8)
C
(8)
C
tD1, tD2 Output Propagation Delay, TTL Inputs
Propagation Matching Between Channels
I
Output Reverse Current Withstand
RVS
(8)
500 mA
Notes:
8. Not tested in production.
9. See Timing Diagrams of Figure 6 and F igure 7.
OUTx at V C
LOAD
OUTx at V C
LOAD
LOAD
LOAD
LOAD
LOAD
(9)
0 - 5VIN, 1V/ns Slew Rate 10 19 34 ns
INA=INB, OUTA and OUTB at 50% Point
/2,
DD
=0.22µF, f=1kHz
/2,
DD
=0.1µF, f=1kHz
2.4 A
-1.6 A
=0.1µF, f=1kHz 3 A
=0.1µF, f=1kHz -3 A
=1000pF 12 22 ns
=1000pF 9 17 ns
1 2 ns
Figure 6. Non-Inverting Timing Diagram Figure 7. Inverting Timing Diagram
© 2009 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN3216 / FAN3217 • Rev. 1.0.2 6
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