Fairchild FAN3122T service manual

FAN3121 / FAN3122 Single 9A High-Speed, Low-Side Gate Driver

FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver

July 2012

Features

 Industry-Standard Pin-out with Enable Input  4.5 to 18V Operating Range  11.4A Peak Sink at V  9.7A Sink / 7.1A Source at V

DD

= 12V

OUT

= 6V

 Inverting Configuration (FAN3121) and

Non-Inverting Configuration (FAN3122)

 Internal Resistors Turn Driver Off If No Inputs  23ns/19ns Typical Rise/Fall Times with 10nF Load  20ns Typical Propagation Delay Time  Choice of TTL or CMOS Input Thresholds  MillerDrive™ Technology  Available in Thermally Enhanced 3x3mm 8-Lead

MLP or 8-Lead SOIC Package (Pb-Free Finish)

 Rated from –40°C to +125°C

Applications

Synchronous Rectifier Circuits

  High-Efficiency MOSFET Switching  Switch-Mode Power Supplies  DC-to-DC Converters  Motor Control

Description

The FAN3121 and FAN3122 MOSFET drivers are designed to drive N-channel enhancement MOSFETs in low-side switching applications by providing high peak current pulses. The drivers are available with either TTL (FAN312xT) or CMOS (FAN312xC) input thresholds. Internal circuitry provides an under-voltage lockout function by holding the output low until the supply voltage is within the operating range.

FAN312x drivers incorporate the MillerDrive™ architecture for the final output stage. This bipolar / MOSFET combination provides the highest peak current during the Miller plateau stage of the MOSFET turn-on / turn-off process.

The FAN3121 and FAN3122 drivers implement an enable function on pin 3 (EN), previously unused in the industry-standard pin-out. The pin is internally pulled up to V

for active HIGH logic and can be left open for

DD

standard operation.

The FAN3121/22 is available in a 3x3mm 8-lead thermallyenhanced MLP package or an 8-lead SOIC package.

VDD

IN

EN

GND

VDD

1

2

3

4

8

7

OUT

6

OUT

GND

5

VDD

IN

EN

GND

1

2

3

4

VDD

8

7

OUT

6

OUT

GND

5

Figure 1. FAN3121 Pin Configuration Figure 2. FAN3122 Pin Configuration

Ordering Information

FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver

Part Number Logic

FAN3121CMPX

FAN3121CMX SOIC-8 Tape & Reel 2,500

FAN3121TMPX

FAN3121TMX SOIC-8 Tape & Reel 2,500

FAN3122CMPX

FAN3122CMX SOIC-8 Tape & Reel 2,500

FAN3122TMPX

FAN3122TMX SOIC-8 Tape & Reel 2,500

Inverting Channels + Enable

Non-Inverting Channels + Enable

Input

Threshold

CMOS

TTL

CMOS

TTL

Package

3x3mm MLP-8 Tape & Reel 3,000

Packing

Method

Quantity per Reel

Package Outlines

Figure 3. 3x3mm MLP-8 (Top View) Figure 4. SOIC-8 (Top View)

Thermal Characteristics

Package

8-Lead 3x3mm Molded Leadless Package (MLP)

8-Pin Small Outline Integrated Circuit (SOIC)

Notes:

1. Estimates derived from thermal simulation; actual values depend on the application.

2. Theta_JL (Θ (including any thermal pad) that are typically soldered to a PCB.

3. Theta_JT (Θ assuming it is held at a uniform temperature by a top-side heatsink.

4. Theta_JA (Θ and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate.

5. Psi_JB (Ψ temperature and an application circuit board reference point for the thermal environment defined in Note 4. For the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6.

6. Psi_JT (Ψ temperature and the center of the top of the package for the thermal environment defined in Note 4.

): Thermal resistance between the semiconductor junction and the bottom surface of all the leads

JL

): Thermal resistance between the semiconductor junction and the top surface of the package,

JT

): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,

JA

): Thermal characterization parameter providing correlation between semiconductor junction

JB

): Thermal characterization parameter providing correlation between the semiconductor junction

JT

(1)

(2)

Θ

JL

1.2 64 42 2.8 0.7 °C/W

38 29 87 41 2.3 °C/W

Θ

(3)

JT

Θ

JA

(4)

Ψ

JB

(5)

Ψ

(6)

JT

Units

FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver

VDD

IN

EN

GND

VDD

1

2

3

4

8

7

OUT

6

OUT

GND

5

VDD

IN

EN

GND

1

2

3

4

VDD

8

7

OUT

6

OUT

GND

5

Figure 5. FAN3121 Pin Assignments (Repeated) Figure 6. FAN3122 Pin Assignments (Repeated)

Pin Definitions

FAN3121 FAN312

2

3 3 EN

4, 5 4, 5 GND

2 2 IN

6, 7 OUT

6, 7

1, 8 1, 8 VDD

P1

Name Description

Enable Input. Pull pin LOW to inhibit driver. EN has logic thresholds for both

TTL and CMOS IN thresholds.

Ground. Common ground reference for input and output circuits. Input.

OUT

Gate Drive Output. Held LOW unless required input is present and V above the UVLO threshold.

Gate Drive Output (inverted from the input). Held LOW unless required input

is present and V

is above the UVLO threshold.

DD

Supply Voltage. Provides power to the IC. Thermal Pad (MLP only). Exposed metal on the bottom of the package; may

be left floating or connected to GND; NOT suitable for carrying current.

DD

is

Output Logic

FAN3121 FAN3122

EN IN OUT EN IN OUT

0 0 0 0 0

0 1

(7)

1

0 1 1

(7)

1

Note:

7. Default input signal if no external connection is made.

(7)

0 0 1 0

(7)

0 1

(7)

0

(7)

0

(7)

1 1

(7)

0

Block Diagram

FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver

V

DD

IN

EN

GND

1

Inverting

100k

(FAN3121)

2

UVLO

V

DD_OK

100k

Non-Inverting

100k

(FAN3122)

V

DD

100k

3

4

Figure 7. Block Diagram

8

V

DD

OUT (FAN3121)

7

OUT (FAN3122)

6

OUT (FAN3121) OUT (FAN3122)

5

GND

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

VDD VDD to GND -0.3 20.0 V

VEN EN to GND GND - 0.3 VDD + 0.3 V

VIN IN to GND GND - 0.3 VDD + 0.3 V

V

OUT to GND GND - 0.3 VDD + 0.3 V

OUT

TL Lead Soldering Temperature (10 Seconds) +260 ºC

TJ Junction Temperature -55 +150 ºC

T

Storage Temperature -65 +150 ºC

STG

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings.

FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver

Symbol Parameter Min. Max. Unit

VDD Supply Voltage Range 4.5 18.0 V

VEN Enable Voltage EN 0 VDD V

VIN Input Voltage IN 0 VDD V

TA Operating Ambient Temperature -40 +125 ºC

Electrical Characteristics

Unless otherwise noted, VDD=12V and TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device.

Symbol Parameter Conditions Min. Typ. Max. Unit

Supply

VDD Operating Range 4.5 18.0 V

IDD Supply Current, Inputs / EN Not Connected

VON Turn-On Voltage 3.5 4.0 4.3 V

V

Turn-Off Voltage 3.30 3.75 4.10 V

OFF

Inputs (FAN312xT)

V

INx Logic Low Threshold 0.8 1.0 V

IL_T

V

INx Logic High Threshold 1.7 2.0 V

IH_T

I

Non-Inverting Input Current IN from 0 to VDD -1 175 µA

IN+

I

Inverting Input Current IN from 0 to VDD -175 1 µA

IN-

V

TTL Logic Hysteresis Voltage 0.40 0.70 0.85 V

HYS_T

Inputs (FAN312xC)

V

INx Logic Low Threshold 30 38 %V

IL_C

V

INx Logic High Threshold 55 70 %V

IH_C

I

Non-Inverting Input Current IN from 0 to VDD -1 175 µA

IN+

I

Inverting Input Current IN from 0 to VDD -175 1 µA

IN-

V

CMOS Logic Hysteresis Voltage 12 17 24 %V

HYS_C

(9)

ENABLE (FAN3121, FAN3122)

V

Enable Logic Low Threshold EN from 5V to 0V 1.2 1.6 2.0 V

ENL

V

Enable Logic High Threshold EN from 0V to 5V 1.8 2.2 2.6 V

ENH

V

TTL Logic Hysteresis Voltage 0.2 0.6 0.8 V

HYS_T

RPU Enable Pull-up Resistance 68 100 134 kΩ

tD1, tD2 Propagation Delay, EN Rising

tD1, tD2 Propagation Delay, EN Falling

(10)

8 17 27 ns

(10)

14 21 33 ns

Output

I

OUT Current, Mid-Voltage, Sinking

SINK

I

OUT Current, Mid-Voltage, Sourcing

SOURCE

I

OUT Current, Peak, Sinking

PK_SINK

I

PK_SOURCE

t

OUT Current, Peak, Sourcing

t

Output Rise Time

RISE

t

Output Fall Time

FALL

Output Propagation Delay, CMOS Inputs

D1, tD2

Output Propagation Delay, TTL Inputs

D1, tD2

I

Output Reverse Current Withstand

RVS

(10)

C

(11)

C

(11)

C

(11)

1500 mA

Notes:

8. Lower supply current due to inactive TTL circuitry.

9. EN inputs have modified TTL thresholds; refer to the ENABLE section.

10. See Timing Diagrams of Figure 8 and Figure 9.

11. Not tested in production.

TTL 0.65 0.90

(8)

CMOS

OUT at V f=1kHz

(10)

0 – 12VIN, 1V/ns Slew Rate 9 18 28 ns

(10)

0 – 5VIN, 1V/ns Slew Rate 9 23 35 ns

0.58 0.85

/2, C

DD

/2, C

DD

=1.0µF, f=1kHz 11.4 A

LOAD

=1.0µF, f=1kHz 10.6 A

LOAD

=10nF 18 23 29 ns

LOAD

=10nF 11 19 27 ns

LOAD

=1.0µF,

9.7 A

7.1 A

mA

DD

FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver

Timing Diagrams

FAN3121 / FAN3122 — Single 9A High-Speed, Low-Side Gate Driver

Figure 8. Non-Inverting Figure 9. Inverting